一種用於三維積體電路電源供應網路的凸塊和矽穿孔錯誤容忍機制

Abstract

三維積體電路可以透過堆疊降低晶片中的繞線長度、面積並且減低晶片中訊號傳輸時間，因此被視為是延續莫爾定律的主要技術。在三維積體電路設計上，需要使用矽穿孔以及凸塊完成不同層晶片之間的連線整合，因此矽穿孔以及凸塊是三維積體電路中重要的一環。然而，現今矽穿孔以及凸塊還是可能因製程上的失敗導致許多問題，為了解決這個問題，本篇論文提出了一個針對供給電源的矽穿孔以及凸塊的錯誤容忍機制。首先，我們以一個快速的方法對矽穿孔以及凸塊在某一個錯誤率下的最壞情況電壓分佈做預測，之後，以用逐步的修整方法來加強原本的電源供應網路，直到壓降值達到設定的目標。我們採用三個分別是基於TSMC180奈米、65奈米以及40奈米製程的實際電路來測試我們的方法，而實驗的結果顯示，我們的方法在針對矽穿孔以及凸塊錯誤容忍的電源供應網補強上是有效的。

Three-dimensional (3D) technology, which provides a way to reduce routing length, footprints, propagation delay through die stacking, has been seen as an important technique to continue Moore's Law. In 3D integrated circuits (3D ICs), Through-Silicon Vias and bumps are employed to integrate dies in different layers. Thus, TSVs and bumps are essential in 3D ICs. However, TSV/bump may fail and cause lots of problems. In order to overcome these problems, in this thesis, a power TSV/bump fault tolerance scheme is proposed. First, we use a fast approach to predict the worst IR-drop distribution under a given faulty rate by analyzing power simulation results. Next, we use an incremental repair method to enhance power delivery network until reaching the given target IR-drop. Our work is experimented on three real designs in TSMC 180 nm, 65 nm, and 40 nm processes. The experiment results show that our methodology is effective in power delivery network enhancement for TSV/bump fault tolerance.