利用田口方法降低系統級封裝在SMT製程之濺錫不良數 - 以X公司為例

Abstract

系統級封裝(System-in-Package，SiP)是系統整合化的構裝，將多種功能不同的晶片、記憶體以及被動元件，經過封裝製程來達到整合的目的，是可縮減封裝體積，節省成本與開發時間之整合方式。在系統級封裝的製程中，表面黏著技術(Surface Mount Technology，SMT)一直是系統級封裝的關鍵製程；藉由表面黏著技術，可將被動元件、已封裝的積體電路(Integrated Circuit)與良裸晶(Known Good Die，KGD)貼裝至高密度的基板(Substrate)上，再經過迴焊及封裝製程後，便可製作出輕、博、短、小的系統級晶片架構。隨著穿戴式裝置與物聯網的興起，對於系統級封裝的需求與日俱增，市場要求構裝尺寸愈來愈小，但系統級封裝的製程良率卻無法提升，所以製程中的不良分析及改善對策愈顯重要。故本論文之主要目的係針對關鍵製程SMT中的濺錫不良之原因進行探討，並利用田口方法，找出可控因子的最佳參數組合，以有效改善製程不良率。本研究最後以台灣半導體封測個案公司之實例，來說明本研究所找出之最佳參數水準組合確實可有效改善該公司晶片堆疊產品SMT製程之濺錫不良之數量。

System-in-Package (SiP) is the package of system integration. It gathers multiple chips, memory and passive components through packaging processes to archieve the purpose of integration. System-in-Package (SiP) could decrease the volume of package, reduce unit cost and speed up product development. In System-in-Package (SiP) manufacturing process, SMT (Surface Mount Technology) is the key process. The objective of this study is to utilize Taguchi method to optimize the SMT manufacturing process. Therefore, this study utilizes signal-to-noise ratio to find the key factors for the solder splash defects during SMT process in System-in-Package. A case study from a semiconductor assembly and test company at Taiwan is utilized to demonstrate that the solder splash defects of stacked die product is reduced effectively employing the optimal parameter-setting values.