應用於多相交錯式三相脈寬調變變頻器之FPGA設計及實現

Abstract

本論文設計和實現應用於三相變頻器之多相交錯式脈寬調變，針對並聯型三相變頻器，分析並以模擬驗證交錯式脈寬調變降低直流鏈電容側和交流負載側電流連波的效果，同時，為了改善並聯型的三相變頻器於低負載電流下，相較於單組三相變頻器效率較低的影響，提出相位脫落控制以改善其效率曲線。其次，在脈寬調變策略中，由於開關導通和關閉並不是即時性的，應用上會加入死區時間以防止開關電路產生短路大電流，然而死區時間會造成非線性的電壓輸出，造成電壓失真和降低有效的輸出電流，而此現象在低調變指標、及高開關頻率和高死區時間會更為明顯。本文針對在不同脈寬調變參考電壓命令造成不同的電壓失真分析並提出適用於不同PWM策略下以載波斜率、電流方向及參考電壓命令實現理想的死區時間補償方案。在FPGA設計實現方面，以兩組直接數位類比轉換器同步於載波波峰波谷回授相電流平均值，以兩組高速上下數計數器實現可調頻之相位移載波，設計不同的零序訊號使程式可產生多種的PWM調變策略，並以直接數位合成器產生高頻率解析度的弦波命令。實驗結果藉由使用SmartFusion A2F200驗證。

In this thesis, the design and implementation of a multiphase-interleaved 3-phase PWM inverter is presented. First of all, analysis and simulation verifications of the ripples cancellation effect to dc-link capacitor and ac load side caused by interleaved PWM are provided. Phase-shedding control to improve efficiency curve at light load condition is presented. Secondly, because the switching components turn on and turn off is not instantaneous, adding the dead-time is required to prevent short circuit. The blanking time will introduce nonlinear output voltage characteristic, which makes the voltage distortion and lower the effective current output. It becomes significant under low modulation index, high switching frequency and long dead-time inserted. Thesis is proposed the dead-time compensation method establishing on carrier slope, current direction and voltage command which is applicable for different PWM strategy. In FPGA design and implementation, two direct analog to digital converters synchronize with carrier peak and valley are used to feedback phase current average value, two sets of high speed up-down counter are used to realize phase-shift carrier signal, different zero-sequence signals are achieved multi PWM strategies, and the direct digital synthesizers is used to generate high frequency resolution sinusoidal commands. Experimental verification has been presented by using SmartFusion A2F200 development board.