奈米級金氧半場效電晶體和鰭狀場效電晶體之隨機擾動訊號及製程變異引致臨界電壓偏移建模化

Abstract

在金氧半場效電晶體和鰭狀場效電晶體中，電子在氧化層和矽通道交界面的釋放和捕捉的現象被稱為隨機擾動訊號，此現象對於奈米級半導體元件的可靠度是一個重要的議題。在這篇論文裡，透過Matlab和三維電腦科技輔助軟體模擬的幫助，我們不但可以重現隨機擾動訊號的實驗量測數據，甚至可以針對金氧半場效電晶體和鰭狀場效電晶體所會遭遇到的擾動震幅做出預測。我們還提出一個mloc-loc邊界線，其中的mloc和loc分別是通道區域電流的平均值和標準差。這個關鍵的mloc-loc邊界線將mloc-loc圖分成允許區與禁止區。允許區內的mloc-loc座標包含了所有可能性，因此我們才能重現出實驗量測數據。不同元件大小與不同的金屬閘極顆粒大小也都必須各有大量模擬。在這份論文裡也考慮了金屬閘極顆粒化功函數擾動，這因素使元件的臨界電壓擾動會更加嚴重。藉由機率統計，我們重現了Intel 14奈米製程的元件數據，並提供電路設計者下個世代隨機擾動訊號的指引。

The trapping and de-trapping of a single electron at the Si-SiO2 interface of planar bulk metal -oxide-semiconductor field effect transistors (MOSFETs) and fin-shape field effect transistors (FinFETs), which is called random telegraph signals (RTSs), has been a well-known issue for the reliability of the nanoscale device. In this work, with the help of Matlab and 3-D technology-aided design (TCAD), we not only reproduce RTS experimental data but also make a prediction of possible worst case threshold-voltage fluctuation amplitude in both MOSFETs and FinFETs. We also propose a mloc-σloc boundary where mloc and σloc are the mean and the standard deviation, respectively, of the channel local current density. The critical mloc-loc curve divides the plot into the allowed and forbidden region. The allowed region includes all possible (mloc, σloc) sets that help us to reproduce experimental data. Furthermore, we take metal gate granularity (MGG) percolation into account. RTS under MGG percolation causes the device threshold-voltage fluctuating more serious. Necessarily, a large number of simulation tasks are carried out to investigate it. Different device sizes and different average metal grain sizes are considered in this work. By statistics, we can finely reproduce Intel’s data and even give a next-generation guide-line for circuit designers.