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dc.contributor.author林于滔zh_TW
dc.contributor.author黃威zh_TW
dc.contributor.authorLin, Yu-Taoen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2018-01-24T07:38:52Z-
dc.date.available2018-01-24T07:38:52Z-
dc.date.issued2016en_US
dc.identifier.urihttp://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070350282en_US
dc.identifier.urihttp://hdl.handle.net/11536/140048-
dc.description.abstract在現今大數據與物聯網的時代,感測器與行動裝置是無所不在的。大量且多樣化的感測器資料使整個系統在蒐集以及儲存資料上遇到挑戰。物聯網路由器迫切的需要一個有彈性的、可控制的、可重複構造的低功率且具有高頻寬的記憶體。此論文針對物聯網應用提出一個用於資料分配單元之可重複構造的多重佇列架構。所提出的架構涵蓋四個部分:接收介面、資料分配單元、連接型多重佇列先進先出記憶體與內部連接網路介面。模擬的實現與成果呈現出只要多付出10.2%的面積,提出的架構就能達到31.3%的產出量提高,所耗損的功率也有7.8%的減少。zh_TW
dc.description.abstractIn the era of big data and Internet of Things (IoT), sensors and mobile devices are ubiquitous. The great number and high diversity of sensor data make the whole system difficult to collect and store these data. A memory system with high bandwidth, flexible, reconfigurable, controllable low power storage is urgent needed for IoT routers. This paper presents a data allocation unit using reconfigurable multi-queue architecture for IoT applications. The proposed architecture consists of four parts: receiver interface, data allocation unit, link-based multi-queue FIFO and network interface. The implementation and simulation results show the proposed architecture achieves up to 31.3% performance improvement and 7.8% power reduction with 10.2% area overhead.en_US
dc.language.isozh_TWen_US
dc.subject物聯網路由器zh_TW
dc.subject面積與功率效率zh_TW
dc.subject可重複構造zh_TW
dc.subject多重佇列zh_TW
dc.subjectIoT Routeren_US
dc.subjectArea-Power Efficiencyen_US
dc.subjectReconfigurableen_US
dc.subjectMulti-Queueen_US
dc.title應用於物聯網路由器之面積與功率效率可重複構造多重佇列架構zh_TW
dc.titleArea-Power Efficiency Reconfigurable Multi-Queue Architecture for IoT Routersen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis