先進電子封裝技術無鉛銲錫與銅界面介金屬化合物的探討

Abstract

先進高階微電子封裝技術發展, 產品朝向外觀微小及性能多功能發展已是必然的趨勢, 在微細間距要求下, 在過去從未遇到的可靠度不佳的狀況, 都變成現在極具挑戰的問題. 本論文旨在研究先進高階微電子封裝製程中無鉛銲錫熔融橋接當中, 銅與焊錫所產生的界面介金屬化合物的變化. 第二章主要在研究以鎳銅雙層架構來當作銅與無鉛焊錫合金- 錫銀焊錫之間的阻隔層的有效性. 本章當中以鎳及鎳銅雙層作為銅與無鉛焊錫合金阻隔層, 來比較鍵合顯微結構的差異, 在過去傳統的銅/無鉛焊錫合金/銅的鍵結架構下, 以單層的鎳來做阻隔層, 只會在鎳與無鉛焊錫合金的界面生成Ni3Sn4界面介金屬化合物. 雖然Ni3Sn4 低成長速率可以減緩鎳與無鉛焊錫合金的消耗, 但大量向銲錫凸塊周圍擴散的錫明顯易見, 錫的向外擴散造成了銲錫凸塊邊緣銅錫界面介金屬化合物的生成, 由於錫的向外擴散導致無鉛焊錫合金內部孔洞逐漸產生, 最後發展成一連續的斷面在鎳與無鉛焊錫合金之間造成積體電路的斷路. 而近年來由於有效降低成本的無鉛焊錫合金技術發展下, 銅與無鉛焊錫合金可以直接接合, 不需要鎳來做阻隔層. 而第三章主要在研究銅凸塊搭配1.8% 錫銀焊錫在可靠度測試不同溫度熱老化過程中, 銅錫界面介金屬化合物的生成狀況. 典型的 Cu3Sn5與 Cu3Sn 界面介金屬化合物在423K熱老化溫度中產生在銅凸塊與1.8%錫銀焊錫界面, 而銅錫界面介金屬化合物在銅凸塊與1.8% 錫銀焊錫界面中產生, 消耗了銅凸塊的銅, 隨著熱老化時間的增加, 在銅凸塊邊緣的錫的取得越發困難, 導致銅錫反應的界面不斷向凸塊內部移動, 反應界面的形狀也從圓錐體截面狀逐漸發展成半球體狀. 當中並從表面擴散與內部擴散的推導來解釋整個熱老化過程中, 形狀的演變. 而第四章主要在研究覆晶封裝焊錫構裝結合中, 二八奈米元件中聚醯亞胺熱處理對錫銀凸塊阻值的影響. 而當中錫銀凸塊阻值的增加, 可以聚醯亞胺熱處理過程中造成除氣的假說加以解釋. 而這些研究期望能對銅與焊錫構裝結合中包含界面介金屬化合物有更清楚的了解. 而對先進高階微電子封裝技術發展與進步有所貢獻

The integration and miniaturization trends in electronic packaging have led to a substantially finer pitch of the device and package lead terminations. Several reliability concerns that have previously not been encountered are currently surfacing. This study investigated the intermetallic layers in Cu/solder joints for advanced electronic packaging from the perspective of solder joint metallurgy. Chapter 2 presents an investigation into the effectiveness of a bilayer of Ni/Cu as a diffusion barrier between the Cu substrate and Sn–1.8 wt.% Ag solder under thermal aging. Experimental analysis and a comparison were conducted primarily on the basis of microstructural examination of the bonding structures, which involved employing a single layer of Ni and a bilayer of Ni/Cu. For a Cu/solder/Cu bonding structure with a single Ni layer, only the Ni3Sn4 phase formed at the bonding interfaces. Although the lower growth rate of the Ni3Sn4 phase reduced the consumption rate of the solder alloy and Ni, pronounced outdiffusion of Sn toward the periphery of the Cu pillar was observed, which formed Cu–Sn IMCs around the periphery of the Cu pillar. Voids formed within the solder layer following the outdiffusion of Sn, and they gradually developed into a continuous gap across the bonding interface, resulting in open-circuit failure. Because the recent cost-cutting measures have enabled the Cu pillar interconnection technique to be used to join the Cu pillar directly to a solder cap without a Ni diffusion layer, Chapter 3 describes an investigation on the Cu pillar capped with a Sn–1.8 wt.% Ag solder to clarify the growth of the Cu–Sn IMCs under thermal annealing at elevated temperatures. Typical Cu6Sn5 and Cu3Sn IMCs that had formed at the interface between the Cu pillar and solder reacted at 423 K (150°C). The formation of the Cu–Sn IMCs at the Cu pillar/solder interface consumed the Cu pillar. With increased annealing times, Sn availability along the sides of the pillar decreased, and thus, the front of the reaction moved to the pillar interior, causing a truncated cone to evolve into a hemispherical front. Lastly, Chapter 4 details our investigation into the effect of the polyimide (PI) thermal process on the bump resistance of flip-chip solder joints for a 28-nm technology device with an aggressive extreme low-k dielectric film scheme and a Pb-free solder. The bump resistance increment was adequately explained with a PI outgassing model devised on the basis of the results of gas chromatography–mass spectrophotometry analysis. The findings are expected to advance our understanding of the intermetallic layers in Cu/Solder joints, eventually resulting in progress in advanced electronic packaging.