混合穿隧式場效電晶體與鰭式場效電晶體的三態內容可定址記憶體電路超低壓應用之研究與分析

Abstract

本論文研究混合穿隧式場效電晶體與鰭式場效電晶體之三態內容可定址記憶體電路在超低壓的應用。我們使用三維TCAD混合模式模擬器模擬電晶體特性，並利用與TCAD模擬結果校準過之HSPICE查表式Verilog-A模型進行電路模擬。進一步將處於近臨界區的混合式電路之搜索延遲時間、動態功率/能量、漏電功耗皆使用穿隧式場效電晶體以及皆使用鰭式場效電晶體的電路做比較。

三態內容可定址記憶體電路利用以隨意項為基礎的漣波比較傳輸架構來改善電路的搜索表現和功率。對混合式三態內容可定址記憶體電路而言﹐比較電路使用穿隧式場校電晶體以改善在低壓時序列連接匹配線的表現﹐並且在其餘部分使用鰭式場效電晶體﹐以減少開關功率和漏功率和更好的電路穩定度。混合式電路在VDD從0.2伏特到0.6伏特之間擁有較快速的搜索時間﹐而在VDD大於0.5伏特時與都使用鰭式場效電晶體的電路擁有較相近的搜索時間。在電壓大於0.35伏特時﹐混合電路和都使用鰭式場效電晶體的電路有相近的漏功率﹐但都較都使用穿隧式場校電晶體電路的漏功率少。而對於動態功率而言﹐混合式電路表現中規中矩﹐擁有比都使用穿隧式場校電晶體電路的動態功率少﹐但比都使用鰭式場效電晶體的電路動態功率還高上一點。

This thesis investigates the hybrid TFET-FinFET implementation of ternary content addressable memory (TCAM) using 3D atomistic Technology Computer Aided Design (TCAD) mixed-mode Monte-Carlo simulation for transistor characteristics and look-up table based Verilog-A model HSPICE simulation. compare the search time, power and energy with all FinFET and all TFET implementations in near-threshold region

The TCAM utilizes a don’t-care-based ripple search line (SL) to improve the search performance and power. In the hybrid design, TFETs are used for comparison circuit to improve the performance and energy of serially connected match line (ML) at low voltage, while FinFETs are used for the rest of the circuit for better cell stability, switching power and leakage power. The hybrid design offers the overall optimized search delay across VDD from 0.6V down to 0.2V, exhibiting search delay close to the (low) all FinFET design for VDD ≥ 0.5V and that close to the (low) all TFET design for VDD < 0.5V. The leakage power of the hybrid design is almost the same as that of the all FinFET design, and lower than that of the all TFET design for VDD > 0.35V. The dynamic power of the hybrid implementation is higher than that of the all FinFET implementation, and lower than that of the all TFET design for VDD from 0.6 down to 0.2V.