應用於W頻帶接收機的65奈米互補式金氧半製程之寬頻鎖相迴路設計

Abstract

現今積體電路技術發展成熟，在微波及毫米波電路設計與製作上使用互補式金屬氧化物半導體(CMOS)取代傳統的III-V族半導體是目前的趨勢。然而，目前使用CMOS製程還有很大的進步空間，因為矽基板在高頻時損耗嚴重，對於高頻應用來說是非常大的缺點，所以設計出高品質因子的被動元件也是必須的。目前晶片多整合成單晶片系統(SoC)，為了解決各個子電路時脈相位不同的問題，需要鎖相迴路(PLL)來減少相位偏差，使系統的時脈相位一致，減低輸出資料的錯誤。

本論文所提出的寬頻鎖相迴路是用台積電65奈米製程所設計，利用開關切換三顆壓控振盪器，再藉由三倍頻器產生壓控振盪器的三倍頻訊號來涵蓋整個W頻帶，提供W頻帶接收機穩定的本地振盪訊號源，此電路將與三倍頻器及W頻帶接收機整合成一顆完整的IC。

論文的第一部分會先介紹寬頻鎖相迴路的幾個基本架構，探討每種架構的優缺點，第二部分則是分別介紹所設計鎖相迴路的子電路，第三部分展示可變電容、壓控振盪器及鎖相迴路的模擬結果和最後鎖相迴路的佈局，最後部分則是論文總結，並說明此設計遇到的難題以及未來的改進方向。

Today's integrated circuit technology is mature, in the microwave and millimeter-wave circuit design and production using complementary metal-oxide semiconductor (CMOS) to replace the traditional III-V semiconductor is the trend. However, there is still a lot of room for improvement in CMOS process, because the silicon substrate in the radio frequency loss is serious, for radio frequency applications is very large shortcomings, so the design of high quality factor passive components is also necessary. Now the chips change to System-on-Chip (SoC). In order to solve the problem of different clock phase of each sub-circuit, a phase-locked loop (PLL) is needed to reduce the phase deviation and make the clock phase of the system coincide and reduce the error of the output data.

In this paper, the proposed wideband phase-locked loop is used TSMC 65-nm CMOS process design, the use of switching three voltage-controlled oscillator, and then by the tripler to generate the third harmonic voltage-controlled oscillator’s signal to cover the entire W-band, to provide W-band receiver stable local oscillator signal source. The circuit will be with the tripler and W-band receiver integrated into a complete IC.

The first part of this paper will introduce the basic structure of wideband phase-locked loop, to explore the advantages and disadvantages of each architecture. The second part is the design of the PLL circuit, the third part shows the variable capacitor, voltage-controlled oscillator and the phase-locked loop simulation results and the layout of the final phase-locked loop. The final part is the paper summary, and that the design problems encountered and the future direction of improvement.