標題: | A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology |
作者: | Yang, Song-Yu Chen, Wei-Zen Lu, Tai-You 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | ADPLL;phase-locked loop;phase accumulator;frequency divider;phase-frequency detector;bang-bang phase detector |
公開日期: | 1-三月-2010 |
摘要: | A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 mu s locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm(2). |
URI: | http://dx.doi.org/10.1109/JSSC.2009.2039530 http://hdl.handle.net/11536/5766 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2009.2039530 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 45 |
Issue: | 3 |
起始頁: | 578 |
結束頁: | 586 |
顯示於類別: | 期刊論文 |