一個 10GHz 快速鎖定之全數位式頻率合成器

Abstract

本論文提出一個具有動態迴路濾波器的10GHz快速鎖定之全數位式頻率合成器。其中，動態迴路濾波器主要由一個鎖定追蹤監測器(Locking Process Monitor, LPM)控制，可在追蹤相位時自動調整迴路濾波器的參數，使得整體迴路頻寬可自動調整直到頻率鎖定。利用此機制可使得整體鎖定時間低於8□s，且當輸出頻率為9.92GHz時，其抖動(jitter)的均方根低於1 ps。在此論文中，並提出一個具偏斜補償的相位累加器電路，使其不只能夠在高速下運作，亦可有低功率的優勢。此論文中的晶片是使用90nm CMOS技術實現，整體晶片面積為0.902mm2，核心電路的部份只佔0.352mm2，使用電壓為1V，消耗功率約7.1 mW，其中數位輸入/輸出單元的電壓為3.3V，消耗功率為2.7 mW

A 10 GHz all digital frequency synthesizer with dynamic digital loop filter is presented. Governed by a locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. Also, the loop bandwidth is self-adjusted to a moderate bandwidth as the loop settles to phase and frequency lock. With less than 8 □sec locking time, the measured rms jitter from a 9.92 GHz carrier is less than 1 ps. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm2, and the chip size including bonding pad is 0.902mm2. The ADPLL core consumes 7.1 mW from a 1V supply, and the digital I/O cells drains 2.7 mW from a 3.3V supply for chip measurement.