一個低功率快速鎖定1.20GHz至6.95GHz全數位式鎖相迴路之實現

Abstract

本論文實現一個低功率快速鎖定且寬幅調整之全數位式鎖相迴路。本鎖相迴路具有兩個運作模式以加快鎖定速度，分別是頻率追捕模式與頻率追蹤模式。在頻率追捕模式中，我們使用習知的假位法(Regula Falsi)加速頻率鎖定的時間，且不論數位控制震盪器之轉移函數具備線性或單調性與否，此運算法皆能成功地進行運算鎖定；在頻率追蹤模式中，我們使用了二階IIR濾波器作為迴路濾波器，期望鎖相迴路在鎖定時輸出能夠更穩定且在相位雜訊中能有更大的衰減量。我們使用壓控振盪器(VCO)和數位類比轉換器(DAC)取代原本迴路中的數位控制震盪器(DCO)，以降低整體鎖相迴路運作的功率消耗。 本電路使用TSMC 90-nm CMOS MSG的製程實現，電路核心面積為0.0561 mm2，整體晶片面積為0.6885 mm2。量測結果顯示在頻率追捕模式中只需花7個參考時脈周期即可完成頻率鎖定；鎖相迴路之輸出頻率範圍為1.20 GHz至6.95 GHz；峰對峰時間抖動值在6 GHz之輸出頻率下為13.8% UI，方均根時間抖動為0.97% UI，所量測之相位雜訊為-57.48 dBc/Hz @1 MHz，-92.98 dBc/Hz @10 MHz，在此輸出頻率下所量測之核心電路功率消耗為10.701 mW

The thesis implements a low-power, fast-locking, and wide-range all-digital phase locked loop (ADPLL). To accelerate the locking time, the ADPLL first operates in the frequency acquisition mode and then in the frequency tracking mode. In the frequency acquisition mode, we adopt the Regula Falsi method for faster frequency-locking. The Regula Falsi method works even the transfer function of DCO is not linear or not monotonic. In the frequency tracking mode, the design uses an IIR biquad two-stage filter as the loop filter to track the input phase and to improve the phase noise. We replace the DCO of the ADPLL with VCO and DAC to reduce the power consumption. The circuit has been implemented in a 90-nm CMOS MSG technology. The core area is 0.0561 mm2 and the whole chip is 0.6885 mm2 with the bonding pads. Measurement results show that it takes 7 reference cycles to lock the frequency in frequency acquisition mode. The output frequency range of the ADPLL is from 1.20 GHz to 6.95 GHz. The measured peak-to-peak jitter and the rms jitter at 6 GHz output frequency are 13.8% UI and 0.97% UI, respectively. At 6 GHz output frequency, the measured phase noise is -57.48 dBc/Hz @1 MHz, and -92.98 dBc/Hz @10 MHz. The ADPLL core consumes 10.701 mW when outputting the 6 GHz output frequency.