| 標題: | VLSI漏電區域的定位與解析 The Location and Root Cause of the VLSI Leakage Path |
| 作者: | 穆劍龍 吳耀銓 Mu, Chien-Lung Wu, Yew-Chung 工學院半導體材料與製程設備學程 |
| 關鍵字: | 失效分析;電性分析;漏電;OBIRCH;InGaAs;Thermal emmi;ASIC;IP;Fourier Transform |
| 公開日期: | 2017 |
| URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070261302 http://hdl.handle.net/11536/140275 |
| 顯示於類別： | 畢業論文 |
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