碳化矽閘式霍爾結構與遷移率暨垂直型金氧半場效電晶體之研究

Abstract

碳化矽做為寬能隙材料，擁有高崩潰電場、高導熱係數及可熱氧化形成氧化層的優點，十分適合應用於高溫高壓的功率元件。但在碳化矽的金氧半電晶體中，由於低品質的二氧化層／碳化矽介面造成了高的介面能態密度，使得通道載子遷移率降低之外，也影響了使用電容—電壓方法量測反轉電荷並萃取載子遷移率的準確性。閘式霍爾量測具有能直接量測到載子在通道移動的實際情形，並萃取反轉層載子濃度及遷移率的優點，因此我們選擇使用此來量測製作出的元件特性。然而，閘式霍爾元件的結構對於靈敏性影響很大，因此適當的結構設計是個重要的課題。此外，在先前的碳化矽金氧半電晶體製程中，接面漏電及擊穿效應一直是造成元件有不正常電性的主因，也是迫切需要改善的地方。本篇論文使用Sentaurus TCAD模擬閘式霍爾元件並找出最佳的設計參數。試片製做中除了使用最佳化的霍爾元件結構外，也針對上述的製程問題進行了改善，實現碳化矽的平面式及垂直式金氧半電晶體。 針對閘極介電層與半導體介面含高介面能態密度的元件，閘式霍爾測量是近年來被廣泛應用的量測方法。然而，霍爾測試結構必須符合一定的設計要件才能準確量測到霍爾電壓，並進一步粹取出載子濃度及遷移率。其中霍爾結構修正參數便代表了霍爾測試結構的量測準確值，可作為不同結構下的準確性評比。在目前發表的文獻中，雖然有不少塊材霍爾測試結構的研究發表，但仍沒有針對閘式霍 爾元件結構的設計研究及量測結果。本論文探討閘式霍爾元件的結構修正參數對元件的影響，並根據模擬結果得到修正誤差小於2%的結構設計參數，十分接近理想的閘式霍爾元件。 在之前的研究中，平面式碳化矽金氧半電晶體的N+型源／汲極與P型井區的接面在逆向偏壓時都有很高的漏電值。這主要是因為在源／汲極的離子植入範圍末端，對晶格造成的損傷無法經由高溫退火製程修復。因此我們調整了源/汲極離子植入的條件，成功降低了對晶格的末端損傷，使得此逆向偏壓漏電值降低為10-11安培以下。 在之前的研究中，垂直式碳化矽金氧半電晶體有N+型源區—P型井區—N-型汲極磊晶層的擊穿效應。這是因為碳化矽的本質濃度很低，加上P型井區的低載子活化率及不完全電離，造成跨在P型井區的空乏區擴張，擊穿效應因而發生。我們除了提高了離子植入的最高能量外，也將目標載子濃度提高了十倍。雖然造成了臨界偏壓些微提高，但也使垂直式碳化矽金氧半電晶體的擊穿效應問題成功解決。將上述兩種製程問題改善後，已能成功製做出可正常運作且電性正常的碳化矽金氧半電晶體。 本次研究中，我們將試片分為乾氧及稀釋一氧化二氮兩種氧化製程，除了量測試片上碳化矽電容的介面能態密度之外，也比較了同試片下平面式及垂直式碳化矽金氧半電晶體電性間的差異。此外，針對改良的閘式霍爾元件分別使用了分離式電壓—電容方法及閘式霍爾量測粹取了反轉層的載子濃度及通道遷移率。根據閘式霍爾量測的結果，顯示在現有的架設下，不需額外安裝具鎖向迴路的量測系統便能成功量測到元件中的典型霍爾效應。本論文也分別使用不同方法粹取得到反轉層載子濃度及通道遷移率，並和介面能態進行比較。

As a wide-band gap material, Silicon Carbide owns the advantages such as high breakdown electrical field, high thermal conductivity and capability of thermal oxidation, so it is suitable for high temperature and high voltage power device applications. However, the poor quality of SiO2/SiC interface leads to a large amount of interface state density, which not only decreases the channel mobility but also results in electrical characteristics extracted from C-V measurements being misestimated. Gated Hall measurements can directly measure the physical kinetic of carriers in the channel, with the inversion carrier density and the channel mobility able to be extracted. However, the geometric parameters of gated Hall device have huge impacts on the measurement accuracy. As a result, the geometric design of gated Hall device should be done for accurate gate Hall measurement. Besides, In the previous SiC MOSFETs fabrication process in our group, junction leakage and punch-through effect are two issues leading to devices with abnormal electrical characteristics, which are urgent to be solved. In this thesis, Sentaurus TCAD is used for gated Hall device simulation, in order to obtain the optimized geometric parameters. For the sample fabrication, the simulation results of gated Hall device are used for masks layout, and the above SiC MOSFETs fabrication issues are also improved, followd by SiC planar MOSFETs and DMOSFETs being fabricated. Gated Hall measurement is widely used in recent years for devices fabricated on semiconductors with high interface state density at the gate dielectric/semiconductor interface. However, Hall testing device should be designed based on some rules for measuring Hall voltage with accuracy, and thus the density and the mobility of carriers can be extracted. Hall geometrical correction factor (GH) is an index assessing the accuracy of the Hall testing structure, which can be treated as the figure of merit as device geometrical parameters are varied. Although there are some publications about bulk Hall testing structure, geometry design and complete measurement results of gated Hall device have not been studied comprehensively. In this work, the impact of geometrical parameters on the measurement accuracy is studied. From the simulation results, the optimized parameter combination to achieve <2% error is proposed, which means the test structure is almost an ideal gated Hall device . In the previous work of SiC planar MOSFETs, there exists a high leakage current at the junction of N+-source/drain region and P-well region at reverse bias. This is mainly due to crystal being damaged at end-of-range of source/drain region during ion implantation cannot be repaired by high temperature annealing. We adjust the multiple ion implantation profile, as a result, the end-of-range damage is efficiently reduced and the reverse junction leakage is reduced to below 10-11 A. In the previous work of SiC DMOSFETs, punch-through effect occurs through N+ (source)/ P-well/ N-epi-layer(drain). This is owing to the low intrinsic density of SiC and the low active carrier concentration in the P-well region, which make the depletion region in the P-well region extend, and thus punch-through occurs. We raise the highest energy and the plateau concentration of ion implantation in the P-well region. As a result, the threshold voltage slightly increases, but punch-through issue is solved. With the aid of these two improvements, SiC MOSFETs with normal electrical characteristics can be fabricated. In this work, gate oxide is grown in dry O2 or diluted N2O ambient for different sample. Interface state density is extracted from MOS capacitor fabricated at the same time, with the electrical characteristics of planar MOSFETs and DMOSFETs being compared and discussed. In addition, gated Hall device is measured by split C-V method and Hall measurement. According to the results, it shows that the measurement set-up without a phase-locked-loop system can efficiently characterize the typical Hall effect occurring in the device. In order to compare the inversion carrier concentration and channel mobility, different extraction methods are introduced, and the relationship between the extracted Dit is also discussed.