鰭狀磊晶穿隧層穿隧電晶體之性能評估及n型磊晶穿隧層穿隧電晶體性能改善之研究

Abstract

磊晶穿隧層穿隧電晶體在低功率應用中被視為具有潛力的元件。在此篇研究之中，吾人藉由Sentaurus TCAD模擬軟體分別評估正型及負型平面磊晶穿隧層穿隧電晶體以及鰭狀磊晶穿隧層穿隧電晶體的性能表現。除此之外，吾人亦提出以固態擴散法取代離子植入法參雜之穿隧電晶體並且實際製作。 於過去研究中，正型及負型磊晶穿隧層穿隧電晶體於模擬中展現陡直的次臨界擺幅以及高導通電流。但鰭狀結構於此研究中無法顯著改善負型穿隧電晶體之性能。鰭狀結構較強的靜電控制能力會使得矽至鍺與矽至矽穿隧電流在低閘極電壓下產生。將閘極電壓為0 V時的閉態電流調整至1 pA/μm 後，增加的閉態電流會劣化負型鰭狀穿隧電晶體之次臨界擺幅，並使負型平面穿隧電晶體的導通電流高出負型鰭狀穿隧電晶體35%。在正型的鰭狀穿隧電晶體中，卻沒有觀察到次臨界擺幅劣化的現象，因為在正型的操作區間中穿隧路徑僅有鍺至矽一條，因此正型平面穿隧電晶體的導通電流比鰭狀穿隧電晶體低40%。 為了改善以鍺作為材料的磊晶穿隧層之磊晶品質，在固態擴散穿隧電晶體中固態擴散法被用以製作無缺陷的正型接面。正型及負型的固態擴散穿隧電晶體皆予以實際製作與討論。雖然這次的鍺磊晶穿隧層成長得並不均勻，過去研究中，嚴重的逆向漏電流於此次實驗中成功地由 10-8 A/μm 降至10-12 A/μm。但固態擴散穿隧電晶體的導通電流因為正型區域濃度不足以及鍺磊晶穿隧層不均勻而較低。導通電流的溫度相關性說明其傳導機制由缺陷輔助穿隧所主導。 雖然鰭狀結構提高了正型穿隧電晶體的導通電流，但同時也劣化負型穿隧電晶體的次臨界擺幅以及導通電流。因此，平面式結構較適合於針對負型操作優化的電路，鰭狀結構較適合於針對正型操作優化的電路。為了要改善固態擴散穿隧電晶體的能帶間穿隧效率並且抑制缺陷輔助穿隧，正型接面的濃度應該予以提升，且極薄的均勻鍺薄膜也是必要的。若能針對上述建議進行調整，固態擴散穿隧電晶體的性能將獲得更進一步的改善。

Epitaxial tunnel layer (ETL) tunnel FET (TFET) has been considered to be one of the promising devices in ultra-low power applications. In this study, the performance of the planar ETL TFET and fin ETL TFET for both n-type and p-type, respectively, are evaluated by Sentaurus TCAD simulation. In addition, TFET that is doped by solid-phase diffusion (SPD) instead of ions implantation was proposed and fabricated. In the previous research, the n-type and p-type ETL TFET show the steep subthreshold swing and high on-state current in the planar structure by TCAD simulation. However, the improvement of the fin structure is not significant in the n-type TFETs (nTFET) in this study. The stronger electrostatic control caused by the fin structure would lead to the Si-to-Ge and Si-to-Si tunneling leakage current at low gate bias. The increased off-state current degrades the subthreshold slope of the fin nTFETand causes the on-state current of the planar nTFET 35% higher than that of the fin nTFET after shifting to Ioff = 1 pA/μm at Vg = 0 V. But the degradation of subthreshold swing is not observed in p-type fin TFET (fin pTFET) because there is only one tunneling path which is Ge-to-Si tunneling at the subthreshold region. Consequently, the planar pTFET shows 40% lower on-state current than the fin pTFET. In order to improve the epitaxial quality of Ge ETL, SPD was applied to form a defect-free p+ junction in the SPD TFET. The SPD TFET was fabricated and discussed for both n-type and p-type. The severe reverse leakage current of nTFET operation in previous research has been suppressed from 10-8 A/μm to 10-12 A/μm successfully though the Ge ETL is non-uniform. But the SPD nTFET still suffers from the low on-state current because of the insufficient concentration of the p+ junction and the poor Ge ETL. The temperature dependence of the on-state current shows that the transport mechanism in the SPD nTFET is dominated by trap assisted tunneling (TAT). Though fin structure improves the on-state current of the fin pTFET, it degrades the subthreshold swing and the on-state current of the fin nTFET as well. The planar nTFET is preferred to be applied in low-power circuits optimized for n-type operation, and the fin pTFET is preferred in the circuits optimized for p-type operation. In the SPD TFET, theconcentration of the p+ junction should be increased to improve the efficiency of band to band tunneling (BTBT). Besides, an ultra-thin uniform Ge layer is necessary to suppress the TAT current. If the above suggestions could be achieved, the performance of the SPD TFET will improve further more.