高電源拒斥比之低壓降線性穩壓器

Abstract

在今日的消費市場中，隨著行動電子產品的蓬勃發展，電源穩壓IC 在行動電子產品電路系統上，扮演著特別重要的角色，且關係到整個系統的性能，一個良好的電源系統，有時甚至就決定了產品的好壞。 本論文所提出之高電源拒斥比之低壓降線性穩壓器，是利用基本的雙級NMOS差動輸入放大器，後面再加一個NMOS的差動電路， 增加增益並改變運算放大器它的頻寬，且選用適合的帶差參考電路產生參考電壓搭配，並再做適當的頻率補償，使整個電路穩定，最後還可獲得較佳的電源抑制比(Power Supply Rejection Ratio, PSRR) 的低壓降線性穩壓器(Low Dropout , LDO)。在模擬Pre-simulation時，電源抑制比可達到≤ - 60dBm ，在模擬Post-simulation時，可達到≤ -50dBm，與傳統標準的低壓降線性穩壓器相比，有相當改善。本論文所呈現之晶片使用台積電所提供之0.35微米2P4M 的標準互補式金氧半導體製程來完成，電路晶片面積為0.8mm×0.767mm。

In recent years, mobile electronic products have become very popular in human life. One more key feature of the mobile electronic product is its power circuit. If the electronic product can be designed with a good power system, the quality of the product can be enhanced. This paper presents a high PSRR LDO regulator which uses a two-stage NMOS differential amplifier combined with a NMOS differential circuit and also chooses a high PSRR bandgap circuit for reference voltage. The circuit can achieve the PSRR lower than ≤ -60dBm and -50dBm during pre-simulation and post-simulation, respectively, which are better than the typical of regular LDOs. The chip presented in this thesis was fabricated by Taiwan Semiconductor Manufacturing Company （TSMC）0.35μm 2P4M 3.3V mixed‐signal CMOS process. The chip area is 0.8mm×0.767mm.