一個帶有冗餘位元每次轉換兩位元的逐漸逼近式類比數位轉換器設計

Abstract

SAR ADC的速度主要受限於最大位元電容電壓的穩定時間以及切換的週期數量。 本論文使用一種適用於每次轉換兩位元全差動式SAR ADC的演算法，並且可以減少50%以上最大電容電壓的穩定時間。我們利用帶有冗餘位元的演算法來自行保有容錯的空間，使其在每個轉換週期時所實際需要等待電壓穩定的時間可以大幅降低。在每次轉換兩位元的架構之中，並沒有使用到其他的高耗能主動元件來產生需要的參考電壓，保持SAR ADC的低耗能的優勢。此外，為了使外部參考時脈不需要過高的頻率以及穩定度，使用了非同步時脈控制電路來產生內部數位電路以及切換轉換週期的時脈。 本論文實現一個9位元類比數位轉換器，行為模型實際可達最高位元為9.18位元，電路模擬結果顯示可達到SNDR為52.84dB，ENOB為8.48 bits。而在最高速也就是delay最短時， SNDR為48.93dB，ENOB為7.84 bits。量測結果顯示在1.8V之下，操作於10MS/s，delay時最長時SNDR為44.72 dB，ENOB為7.14，電流消耗為1.05mA(類比部分)以及0.28mA(數位部分)；而delay時最短時SNDR為46.65 dB，ENOB為7.46，電流消耗在35MS/s時為1.05mA(類比部分)以及0.97mA(數位部分)。

The speed of SAR ADC is limited by settling time of MSB capacitor and number of converting cycle. This thesis implemented a two-bit/step algorithm for fully differential SAR ADC, and reduce over 50% settling time of MSB capacitor. We use redundant bits to self- tolerate the mistake of settling. Since one of SAR ADC’s advantage is low power consumption, we design a reference voltage generator without component which cost lots of power to fit the two-bit/step architecture. To avoid the need of inputting a high-frequency clock externally, the asynchronous clock is used. We design a 9-bit SAR ADC. and the behavior model shows that it could achieve 9.18b ENOB. The circuit simulation results achieve 52.84dB SNDR, 8.48b ENOB. In the least delay case, the results achieve 48.93dB SNDR, 7.84b ENOB. The measurement results achieve 44.72dB SNDR and 7.14b ENOB, It consumes current of 1.05mA(analog part) and 0.28mA(digital part) at 1.8V supply voltage with the longest delay time in 10MS/s. And achieve 46.65dB SNDR and 7.46b ENOB, It consumes current of 1.05mA(analog part) and 0.97mA(digital part) in 35MS/s with the shortest delay time.