十二位元每秒兩千五百萬次取樣非同步連續近似類比數位轉換器及其全數位校正機制

Abstract

連續近似類比數位轉換器(SAR ADC)的解析度主要受限於因製程變異而造成的匹配誤差。以往已經有人提出前景和背景校正[1][2][3][4][5]來提昇SAR ADC的解析度，但兩者都有各自存在的缺點。前景校正利用電荷守恆的原理，電路實現上比較簡單，但電容誤差會因環境參數的變異而導致校正失敗；背景校正可以克服環境參數的變異但是要用電路實現複雜的數學公式，會讓整個SAR ADC在速度和耗能表現上大打折扣。 本篇論文提出的校正方法，集合前景和背景校正的優點，在提昇SAR ADC的解析度的同時，減少對速度和耗能表現上的影響。另外，我們選用適合的電容切換方法使比較器的設計簡單化以提升其性能。 後佈局模擬結果顯示，當DAC上每個電容存在隨機誤差時，SAR ADC在校正前的 SNDR為47.4dB，校正後SNDR提昇到63.9dB。量測結果顯示SAR ADC在其最高取樣頻率10MS/s下，校正前的SNDR為47.1dB，校正後SNDR提昇到51.8dB。

The resolution of a SAR ADC is mainly limited by the accuracy of capacitor ratios. Foreground and background calibration schemes [1][2][3][4][5] have been proposed to calibrate the capacitor weight errors. However, both kinds of calibration schemes may suffer from power and speed penalties. The foreground calibration schemes using charge redistribution have the advantage of simple implementation but the continuous variations of environmental parameters may cause it failed. The background calibration schemes can address the variation problems but its hardware is very complicated due to the implementation of complex mathematical equations. This thesis proposes a calibration scheme that keeps the advantages of the foreground and background calibration schemes and improve the performance of the SAR ADC in power and speed. We also adopted a suitable bit-cycling scheme to simplify the comparator design and thus to enhance its performance. Post-layout simulation results show that the calibrated SAR ADC achieves a SNDR improvement from 47.4dB to 63.9dB at a sampling rate of 25MS/ s when random mismatch is added on each capacitor in DAC. Measurement results shows the SAR ADC achieves a SNDR improvment from 47.1dB to 51.8dB at its highest sampling rate of 10MS/s.