一個十二位元每秒兩千五百萬次取樣具非同步時脈產生器與全數位校正機制之連續近似類比至數位轉換器之實現

Abstract

SAR ADC的解析度主要受限於製程製作出的電容比例是否精確。本論文使用一種適用於全差動SAR ADC的全數位校正方法實現一個十二位元每秒兩千五百萬次取樣之非同步連續近似類比至數位轉換器。對於一個由已知比例關係構成的待校電容陣列，我們使用該全數位校正法估測待測電容的真正權重，並將之數位化後加以儲存。接著藉由所儲存之權重校正轉換結果達到校正的目的。該全數位校正方法不論電容值比設計值高或低，皆可以正確地估算權重與補償權重誤差，提升SAR ADC的有效位元數。此外，我們設計了一個非同步時脈產生器以避免需要由晶片外部輸入高頻時脈的問題。 電路模擬結果顯示，若加上電容隨機誤差，校正前此ADC的SNDR=32.67 dB，ENOB=5.13 bits，校正後SNDR=60.29 dB，ENOB=9.72 bits，可大幅改善因電容間不匹配所造成的非線性。本設計已使用90nm CMOS實現。實作晶片量測結果顯示，未校正時當取樣頻率為8MS/s時，SNDR=43.66 dB，ENOB=6.84 bits，校正後SNDR=52.96 dB，ENOB=8.48 bits。

Mismatched capacitors in the DAC due to process variations limit the resolution of a conventional capacitive SAR ADC. This thesis implemented a digitally calibrated fully differential SAR ADC. The adopted calibration scheme first estimates the real weights of the capacitors under calibration in the binary-weighted capacitor array. Then, the real weights are digitized and stored. After weight estimation, the SAR ADC calibrate the output codes according to the stored weight table to enhance the accuracy of the SAR ADC. The adopted calibration scheme is able to calibrate the weight errors of the capacitors under calibration, no matter they are positive or negative. To avoid the need of inputting a high-frequecy clock externally, the proposed asynchronous clock generator is used. Simulation results show that the calibrated SAR ADC achieves an SNDR improvement from 32.67dB to 60.29dB at a sampling rate of 25MS/s when random weight errors are added to the capacitors in the DAC. Measurement results show the SAR ADC achieves an SNDR improvement from 43.66 dB to 52.96 dB at a sampling rate of 8MS/s.