具穿隧式電晶體與金氧半場效電晶體異質結構之超低能耗數位邏輯與非同步電路設計

Abstract

穿隧式電晶體(tunnel field-effect transistor, TFET)被視為可提升電路功耗效能的新穎電晶體，藉由能帶間穿隧(band to band tunneling)的特殊電流導通機制，在低電壓的區間可進一步達到快速開關、低次臨界擺福(subthreshold swing)等特性，但低效能的能帶間穿隧，卻也導致低導通電流現象，進一步限制了穿隧式電晶體在高速電路上的應用，磊晶穿隧層穿隧電晶體(epitaxial tunnel layer TFET)的新穎電晶體架構因而被提出，透過使用SiGe異質低能隙材料於磊晶穿隧層，在維持低關閉漏電流的前提之下，可進一步降低次臨界擺福以及提升導通電流，而磊晶穿隧層穿隧電晶體可與目前主流的金氧半場效電晶體製程相容，提供了穿隧電晶體與金氧半場效電晶體異質設計的可能性，本論文針對30奈米製程的磊晶穿隧層穿隧電晶體以及30奈米製程的全空乏絕緣上覆矽(fully depleted SOI)金氧半場效電晶體的電路表現進行比較，進而提出穿隧電晶體與金氧半場效電晶體異質邏輯設計於超低能耗非同步電路應用上的優勢，在五個主要展示的非同步電路管線化階段邏輯設計(asynchronous pipeline stage logic)上，可達到20.9\% - 33.9\%的功耗節省。

The tunnel field-effect transistor (TFET) is a promising solution for high energy-efficiency circuits. The unique band to band tunneling (BTBT) conduction mechanism is used to achieve fast switching characteristics with a steep subthreshold swing (S.S.) in low voltage operation. However, the inefficiency of BTBT results in low on-state current and limits the application of TFET-based circuits. A novel TFET structure with an epitaxial tunnel layer (ETL) is proposed. Through the use of SiGe low band gap material in ETL, the S.S. and on-state current can be further improved without current leakage. ETL-TFET enables the heterogeneous integration of TFET and MOSFET in current CMOS technology to leverage the benefits of both technologies. This work compares the circuit performance between 30nm ETL-TFET and 30nm fully depleted SOI (FDSOI) MOSFET. By combining the circuit advantages of TFET and MOSFET, heterogeneous TFET-MOSFET logic gates are proposed for asynchronous datapaths to enhance energy efficiency. A 20.9\% - 33.9\% energy consumption reduction is achieved in five asynchronous pipeline stage logics.