應用於漸進式時序驅動擺置法的早期延遲與晚期延遲最佳化方法

Abstract

在RTL至GDSII VLSI設計流程中，placement的結果對於timing的問題往往扮演著重要的角色，一個placement timing的好壞著重在early slack和late slack兩大指標上，在本篇論文中，處理early violation時，主要將violation的flip flop移動到距離前一顆cell較遠的位置，或是將violation flip flop的前一顆cell移動到距離較遠的位置，針對late violation的部分，將違反timing的路徑做改善，針對路徑上的cell利用我們設計的cost function在一個windows下做local search移動，違反timing的cell將會被移動到local optimize的位置上，最終實驗在2015 ICCAD前三名placement的結果上，對他們的placement加以改善，透過我們的演算法能讓最終的結果在短距離下整體的總分改善87.35%，長距離下平均總分改善58.7%，early slack、late slack、以及average bin utilization都比原先前三名還要好。

In the RTL to GDSII VLSI design flow, placement step often plays an important role in timing driven placement problem. Early slack and late slack are mainly discussed in the timing problem during placement stage. In this paper, for the early violation, we move each flip flop with violation to the new location, which is far away from its parent cell. For the late violation, we collect the worst path cell from the late violation flip flop, compute the cost function under the local search windows, and move the cell with violation to the local optimized location. Based on the final experiment comparison with the top three results in ICCAD contest 2015, the overall result of the proposed algorithm in short term is averagely improved by 87.35%, those in long term is averagely improved by 58.7%. Besides early slack, late slack and average bin utilization are all better than the results of the top three winners of CAD contest.