垂直堆疊N型多晶矽無接面奈米線電晶體及其串聯電阻

Abstract

垂直堆疊奈米線電晶體被視為最具有潛力實現三維積體電路的元件。在本篇研究中，垂直堆疊奈米線電晶體搭配低熱預算的高介電係數氧化層金屬閘極也被成功製作出來。然而，對於垂直堆疊的結構而言，隨著堆疊層數增加其開啟電流(Ion)不成比例上升的現象也以實驗驗證出來。 首先，奈米線是否可以完全懸空及其經過熱處理過後的基本電特性比較已被完整探討。其中，RTA_500℃_H2/N2_30s這個條件其開啟電流可以由0.81uA增加到1.02uA同時使臨界電壓（Vt）及最低關閉電流（Imin）保持不變。另一方面，次臨界擺幅(subthreshold slope，S.S.)及汲極引致能障下降(DIBL)也分別由278mV/dec到226mV/dec。最後，由水平多通道歸一化的後的串連電阻值可以發現其值約在5x105Ω-um。這結果顯示出水平多通道的開啟電流是可以被線性提升的。 接下來，垂直堆疊奈米線電晶體搭配低熱預算的高介電係數氧化層金屬閘極已被成功製作出來。由電性結果可以發現單位截面積下的電流可以隨層數上升而有效地增加，由1.24uA到1.83uA。然而，次臨界擺幅(subthreshold slope，S.S.)及汲極引致能障下降(DIBL)則會有些微的劣化。另一方面，介電層沉積後熱退火（PDA）與介電層沉積後電漿氧化（PPO）的比較也以實驗證實。由電性分析可以發現因為較好的介面特性導致PDA的開啟電流1.22uA比PPO的1.02uA高。且次臨界擺幅(subthreshold slope，S.S.)及汲極引致能障下降(DIBL)也因為較好的介面特性而有顯著改善，由370mV/dec 到 143mV/dec。此外，利用三種不同的方法來分析垂直堆疊結構的串聯電阻議題也以實驗結果展示。由於底層的元件比上層的元件其載子需要跑更遠的距離，導致堆疊結構的電流無法隨層數增加而線性提升。 最後，綜合以上研究結果 （一） 水平多通道的結構並不會受到串聯電阻的影響，因此其開啟電流可以隨通道增加而線性上升。 （二） 垂直堆疊的結構可以有效地增加單位面積下的開啟電流但會伴隨著些微次臨界擺幅(subthreshold slope，S.S.)及汲極引致能障下降(DIBL)的劣化。 （三） 對於堆疊結構而言，底層的載子傳輸需要較遠的距離導致其串聯電阻較大。因此單位面積下的開啟電流無法隨層數上升而等比例的增加。

Vertically stacked nanowire transistors are considered as the most promising candidate to fulfill the concept of three dimensional integrated circuits. In this research, the vertically stacked nanowire transistor has been successfully fabricated. Moreover, the high-k metal gate was introduced owing to the merits of low thermal budgets. However, the disproportional phenomenon of drive current enhancement with increment of layers caused by the series resistance issue for vertically stacked structure has been experimentally addressed. First of all, the fully suspended nanowire transistor was successfully fabricated for demonstration purpose and the electrical transfer characteristics with four different thermal treatments were also discussed. For RTA_500℃_H2/N2_30s, the drive current (Ion) under the same over-drive of 2V improves from 0.81uA to 1.02uA. Furthermore, this condition also leaves the threshold voltage and Imin unchanged. On the other hand, the subthreshold characteristics of S.S. and DIBL also improves from 278mV/dec to 226mV/dec, respectively. Finally, the normalized series resistance for channel counts of 2, 10 and 20 is nearly the same and the value is around A, B and C respectively. Therefore, the drive current can be enhanced proportionally. Next, the vertically stacked nanowire transistor was fabricated with the introduction of high-k metal gate for low thermal budget purpose. The drive current per footprint can be effectively enhanced with the increment of layers from 1.24uA to 1.83uA. However, the subthreshold characteristics of S.S. and DIBL were slightly degraded with the increment of layers. Moreover, the comparison between PDA and PPO treatment were also conducted. The drive current (ID) of PDA of 1.22uA is higher than PPO of 1.02uA due to the interface quality and improved subthreshold swing under the same over drive of 2V. Moreover, the subthreshold characteristics of S.S. and DIBL also improves from 370mV/dec to 143mV/dec, respectively. Eventually, the series resistance issue was experimentally demonstrated by three different approaches. The analysis shows that the series resistance of bottom layer is definitely larger than upper layer which cause the disproportional phenomenon of drive current enhancement with the increment of layers.