透過早期子電路模擬效能來實現類比電路佈局的方法研究

Abstract

由於在先進製程下無法精準地預測電路的效能，IC 佈局的生成對於設計者來說仍具有相當的挑戰性。然而，我們可以重複利用先前的佈局結果或樣板來減少現階段擺放類比電路模擬差異。在這篇論文中，基於幾何保存和使用者定義的限制以及現存樣板，我們提出了一個實際的方法和多階層流程來合成佈局。電路限制會在分群和佈局列舉階段被優先處理。此外，我們執行了可替換的子電路層級的後期模擬並所將得到的模擬數值整合到佈局列舉中的成本函數。實驗結果顯示此方法可以產生出有效的類比電路，其效果接近或者更優於來自有經驗使用者的手動佈局或是遷移佈局。

The development of analog IC layout generation remains challenges to IC designers due to the imprecise estimation of circuit performance in advanced technology. However, the previous layout results or templates can be reused for the purpose of closing the simulation gap in current analog placement generation. In this work, a practical methodology as well as hierarchical flow is proposed to synthesize layout solutions based on the geometric preservation of user-defined constraints and existing templates. The constraints of the circuit are priorly tackled in the partition and layout enumeration stage. In addition, we perform replaceable subcircuit-level post-simulation and integrate the simulation factors into the cost function in the layout enumeration strategy. The experiments show that this flow yields valid analog layout results whose performances are near or even better than the layouts implemented by experienced designers or migrated layouts.