使用多屬金屬線段並有效節省功耗與面積之保持時間修正技術

Abstract

在晶片設計中，保持時間修正技術是必不可缺的步驟，因為它確保了資料同步的正確性，也因此，在整個設計過程中擔當最後一步的看守者的角色。通常我們會放置緩衝器來進行保持時間違規的修正。然而在整個晶片設計的最後階段，修正保持時間時必須面對大量瑣碎而分散的微量違規線路，面對這個情況，使用緩衝器來修正有以下的缺點：首先，緩衝器會使繞線難度增加，占用更多空間，並導致漏電功率增加。第二，由於空間限制，擺置引擎可能將緩衝器放在遠離違規線路的位置，從而引發另一輪的保持時間修正或需要晶片設計者進行手動修正。因此，在本論文中，我們提出通過多餘金屬線段來修復最後的保持時間違規，達到一個更有效率的功耗使用來延長便攜式設備的使用時間。在時序收斂的最後一步，多餘金屬線段和違反保持時間的線路都分散在整個晶片之中。因此，我們選擇使用最低成本網絡流量演算法來分配適當的多餘金屬段修正違反的線路。我們的實驗進行在六種智慧型手機部分電路設計，這六個電路皆採用台積電16奈米製程。我們的研究結果顯示，與傳統的緩衝器放置法相比，我們的方法可以減少37％的保持時間緩衝器放置空間，在時序收斂的最後一步仍可達到節省漏電功率並盡量的降低空間使用。

Hold time fixing ensures correct data synchronization, which is essential and serves as the final step of timing closure for IC design. Conventionally, buffer insertion is adopted to fix hold time violations; however, in last step of hold time fixing, leave numerous nets with small violation, buffer insertion have disvantage as follow: First, buffers induce routing difficulty, increase area utilization, and contribute leakage power. Second, due to area limitation, placer may put buffer far away from violation path, which induce another hold time fixing iteration. Therefore, in this thesis, we propose to fix hold time violations by free metal segment allocation for achieving leakage power efficiency and maintaining utilization for mobile and portable devices. At the final step of timing closure, free metal segments and hold violating nets are both fragmented and scattered over the design. We thus perform minimum cost network flow to assign proper free metal segments to hold violating nets. Our experiments are conducted on six industrial smartphone designs with TSMC 16nm process, and our results show that compared with the conventional buffer insertion method, our approach can reduce 37\% hold time buffer area, promising for saving leakage power and maintaining area utilization—suited to the final step of timing closure.