製備銦鎵鋅氧化物濺鍍靶材及薄膜電晶體與 透明電阻式記憶體之應用研究

Abstract

本研究混合商用氧化銦（In2O3）、氧化鎵（Ga2O3）與氧化鋅（ZnO）粉體，再利用機械研磨法搭配化學分散法製成奈米級粉體，探討其製成兩吋直徑、單一相InGaZnO4（IGZO）濺鍍靶材的最佳燒結溫度與時間，接著將濺鍍沉積所得之非晶IGZO（a-IGZO）薄膜應用於薄膜電晶體（Thin-Film Transistor，TFT）中的主動通道層（Active Channel Layer）與全透明電阻式記憶體（Transparent Resistive Random Access Memory，TRRAM）中的電阻轉換層（Resistive Switching Layer，RS），並完成TFT與TRRAM的元件特性、微觀結構與組成的分析。論文研究區分為三部分，概述如下。 第一部分利用機械研磨法搭配不同比率的聚甲基丙烯酸（Poly(methacrylic Acid，PMAA）化學分散劑進行In2O3、Ga2O3與ZnO混合粉體的研磨，實驗結果顯示添加3 wt.%的PMAA分散劑可獲得含平均粒徑約為53 nm奈米粉體，將其乾燥、過篩、壓製成綠胚，經1300C、6 hrs大氣環境的無壓力燒結（Pressure-less Sintering）後，可獲得單一相、相對理論密度為93 %的IGZO濺鍍靶材。 第二部分將自製的IGZO靶材以濺鍍法沉積a-IGZO薄膜以做為TFT元件中的主動通道層，並研究退火溫度對TFT元件傳輸特性的影響。實驗結果顯示，經300C、1 hr大氣環境退火之TFT元件有最佳的電氣性質，其飽和載子遷移率（Saturation Carrier Mobility，sat）為14.7 cm2V1sec1、臨界電壓（Threshold Voltage，Vth）為0.57 V、次臨界擺幅（Subthreshold Swing，S.S.）為0.45 Vdecade1、電流開關比（On-Off Ratio或Ion/Ioff）為108。濺鍍過程的氣體流量比對TFT元件特性的影響亦研究之，實驗結果顯示以氬（Ar/O2）比為2.0 :0.6沉積的a-IGZO薄膜製備的TFT元件特性最佳（sat = 5.1 cm2V1sec1；Vth = 1.2 V；S.S. = 0.8 Vdecade1；Ion/Ioff = 5×106）。本項研究亦製備金屬/氧化物/半導體與金屬/絕緣層/金屬兩種結構，量測其電容-電壓及電流-電壓曲線推論TFT中的體缺陷及界面缺陷密度（Interfacial Trap Density，Dit），實驗結果顯示適當的退火熱處理可有效地降低Dit值，從而提升TFT的元件特性。 第三部分的研究將a-IGZO薄膜做為RS層、搭配銦錫氧化物與銦鋅氧化物薄膜透明電極製成TRRAM，實驗結果顯示，此一元件的可見光波段光穿透度超過80%，經300C、1 hr大氣環境退火的元件展現最佳記錄特性（VSET = 0.6；VRESET = 0.7 V；RHRS/RLRS（電阻比值）> 103）且不需施加形成電壓（Forming-free），循環壽命及資料保存能力測試顯示其記錄次數逾106次，且經104秒後電阻比值仍維持不變。為釐清TRRAM之操作機制，在不同氣壓環境下的電性量測結果顯示，當環境真空度降低至1 mtorr時，TRRAM元件之臨界電壓（VSET與VRESET）值顯著下降，此乃因氧分壓降低時，RS層中的氧空缺（Oxygen Vacancy， ）與載子數量同時提高，其提供穩定數量的導電細絲而使電荷捕捉/解補機制更為容易進行。此一量測證實TRRAM之運作應由電荷捕捉/解補機制主導，並能藉由調控 數量而提高其元件效能。

A hybrid process of mechanical grinding and chemical dispersion was adopted to fabricate the nano-scale In2O3, Ga2O3, and ZnO powders for the preparation of 2-inch, single-phase InGaZnO4 (IGZO) sputtering target. The amorphous IGZO (a-IGZO) layers were then deposited by utilizing the self-prepared IGZO target and separately served as the active channel layer of thin-film transistor (TFT) and resistive switching (RS) layer of fully transparent resistive random access memory (TRRAM) devices. The operational properties, microstructures and compositions of devices were analyzed. The experimental works are divided into three parts and briefly described as follows. In first part of study, poly(methacrylic acid) (PMAA) was adopted as the chemical dispersant to prepare the nano-scale In2O3, Ga2O3, and ZnO powders via a hybrid process of mechanical grinding and chemical dispersion. By adding 3 wt.% of PMAA in the suspension, the nano-scale oxide powders with the mean particle size (d50) about 53 nm could be achieved. Consequently, the single-phase IGZO sputtering target with theoretical density of 93% could be obtained via the pressure-less sintering at 1300C for 6 hrs in air ambient. In second part of study, TFT devices containing a-IGZO as the active channel layers were prepared by sputtering deposition within above-mentioned IGZO target. Electrical characterizations indicated that the best device performance with saturation mobility (sat) of 14.7 cm2V1sec1, threshold voltage (Vth) of 0.57 V, subthreshold gate swing (S.S.) of 0.45 Vdecade1 and on-off ratio (Ion/Ioff) of 108 could be achieved in TFT sample subjected to a post annealing at 300C for 1 hr. The influence of Ar/O2 inlet gas flow ratios of sputtering process on TFT performance was also investigated and the best electrical properties (sat = 5.1 cm2V1sec1, Vth = 1.2 V, S.S. = 0.9 Vdecade1 and Ion/Ioff = 5106) was observed in TFT prepared at the Ar/O2 inlet gas flow ratio of 20:0.6. In order to clarify the influence of defect structures on device performance, the metal-oxide-semiconductor (MOS) and metal-insulator-metal (MIM) structures were prepared. It is illustrated that appropriate post annealing might suppress the interfacial traps density (Dit) to promote the TFT performance. In third part study, TRRAM containing a-IGZO as the RS layer and indium tin oxide and indium zinc oxide transparent conducting oxides as the electrodes were prepared. The transmittance of TRRAM exceeded 80% in visible-light wavelength range. The TRRAM exhibited the forming-free feature and the best electrical performance (VSET = 0.61 V; VRESET = 0.76 V; RHRS/RLRS (i.e., the R-ratio) > 103) was observed in the device subject to 300C annealing for 1 hr. Such a sample also exhibited satisfactory endurance and retention properties as revealed by the reliability tests. The TRRAM could operate more than 106 times and maintained its R-ratio after 104 sec of test. The electrical properties were measured in the ambient with various atmospheric pressures for clarify the role of oxygen vacancies ( ) in the RS behaviors of TRRAM. The decrease of pressure implied the increasing number of in RS layer, meaning the number of charge carriers in RS layer would simultaneously increases. The abundance of charge carriers facilitated the formation of conduction filament and, accordingly, promoted the charge trapping/de-trapping process. This demonstrated that the RS mechanism in our TRRAM closely relates to the charge trapping/de-trapping processes and the modulation of content in RS layer might enhance the TRRAM performance.