考量時脈下異質型FPGA之增量式叢集

Abstract

隨著科技日新月異，在FPGA架構及電路都愈漸複雜之下，叢集和佈局兩個電子設計自動化的步驟越顯得重要，其結果都將影響最後繞線的品質以及電路的效能。 在叢集的這個步驟中，在同時考量邏輯相關的電路聯繫以及時脈配置的狀況下將電路的基礎元件包裝進可設定邏輯區塊中，並嘗試極小化可設定邏輯區塊的數量和外部的繞線。 而現代的異質型FPGA架構中，除了基本的輸入輸出元件區塊、可設定邏輯區塊外，還有嵌入式的記憶體區塊和數位訊號處理區塊，在佈局階段需要針對這些根據資源的分布來做功能的調整及優化。 此外，FPGA多重時脈的繞線架構也是會對佈局有許多的影響，需要在叢集和佈局階段對其做額外的考慮。

在這篇論文裡，我們提出了一個使用增量式叢集方法的異質型FPGA擺置器。在叢集階段，我們對所有元件進行快速的初步佈局，接著藉由交替的佈局及叢集並同時考量正反氣的控制訊號、時脈的分布和繞線的狀況來對基礎元件根據其相關密切性進行叢集。 而在佈局階段，我們採用了線長驅動的全域擺置器，其中有許多針對異質型FPGA架構來進行調整的技巧，包含 (1)針對複雜邏輯元件進行位置校正、 (2)藉由全域性繞線器預估壅塞程度來進行區塊動態叢集/分割、 (3)針對多重時脈進行動態時脈規劃 ，最後藉由佈局遷移法、佈局佈局合法化及詳細佈局完成整個擺置器。 實驗結果顯示以上所述之方法皆可有效率的提升佈局的品質。

Packing and Placement are two crucial stages for FPGA implement. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic units are clustered in the packing stage has a great impact on the placement quality.

This work introduces an analytical placement framework for heterogeneous FPGAs through an incremental packing algorithm. In the packing stage, we first perform a fast wirelength-driven placement for the basic logic units. From the initial placement solution, we alternatively implement affinity-based clustering and placement with gradually shrinking legalization force while taking the control signal constraints into consideration.

In the placement stage, a quadratic global placer is implemented with the techniques of handling the heterogeneity, routing congestion estimation by a global router and congestion-driven packing$/$unpacking. An incremental placer is performed after the global placement for closing the gap between global placement and detailed placement. Legalizer and detailed placer are adopted to legalize the blocks and furtherly reduce the wirelength. Experimental results show that the proposed methodologies can effectively improve placement solutions.