完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 曲崇銘 | zh_TW |
dc.contributor.author | 李威儀 | zh_TW |
dc.contributor.author | Chu, Chung-Ming | en_US |
dc.contributor.author | Lee, Wei-I | en_US |
dc.date.accessioned | 2018-01-24T07:41:54Z | - |
dc.date.available | 2018-01-24T07:41:54Z | - |
dc.date.issued | 2017 | en_US |
dc.identifier.uri | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070082007 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/142181 | - |
dc.description.abstract | 由於一般三五族半導體,氮化鎵、砷化鎵,缺乏自然生成的高品質氧化層,不若矽半導體有很好的高品質氧化矽,因此借助高介電係數介電層當做高閘極介電層是有需要的。然而三五族半導體與高介電係數介電層屬不同材質成長,由於異質結合及晶格不匹配,因此在表層含有大量缺陷。這對於高介電係數介電層不管應用在在金氧半電晶體當做高閘極介電層,或應用在金屬-絕緣體-半導體的閘極結構高電子遷移率電晶體當做漏電阻擋層,皆會對元件特性產生極大的衝擊。因此本論文先以結構簡單的金氧半電容元件研究堆疊式氧化層結構高介電係數介電層的可靠度,施予垂直電場電性應力,以檢測在垂直電場電性應力作用下,研究缺陷形成機制及介電層壽命。矽半導體的可靠度分析方法皆可應用在化合物半導體。接下來擴展到三端的元件,堆疊式氧化層結構來製作金屬絕緣層氮化鎵高電子遷移率電晶體,同時施予水平及垂直電場電性應力,以檢測在水平及垂直電場電性應力作用下,研究缺陷如何影響元件特性及壽命。第三部份藉由三端的元件失效的機制,進一步研究堆疊式氧化層結構來製作金屬絕緣層氮化鎵電容元件,閘極絕緣層可靠度壽命。電流傳導機制的衰退及介面缺陷的變化皆予以探討。 | zh_TW |
dc.description.abstract | Lacking high quality natural oxide films would be a problem for those devices built by III-V compound semiconductor, such as GaAs and GaN, They don’t have natural oxide films, such as SiO2 for Silicon, to form gate oxide film. It’s necessary to look for high-κ dielectric film as replacement. But the interface exist lots of traps between semiconductor and high-κ dielectric film due to lattice mismatching from hetero-epitaxial structure. This problem will impact the device performance for MOSFET which uses high-κ film as gate oxide, or MIS-HEMT ( metal insulator semiconductor high electron mobility transistors ) which uses high-κ film to improve gate leakage. This thesis studies the reliability, finds the failure mechanism, and evaluates the lifetime on stacking high-κ dielectric design in III-V compound devices. The first portion starts on simple MOS capacitor structure with stacking high-κ films to investigate the time-dependent dielectric breakdown (TDDB) characteristics and trapping mechanism by applying vertical voltage stress. Silicon based reliability analysis method could be as a reference to be applied on compound semiconductor, The second portion extends to 3 terminals MIS-HEMTs to evaluate the lifetime and trapping effect by applying both vertical and horizontal voltage stress. The third portion further studies MIS capacitor with stacking high-κ films based on failure mode in the second portion. Degradation on current transportation mechanism and interface traps density (Dit) will be discussed. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 氮化鎵 | zh_TW |
dc.subject | 砷化鎵 | zh_TW |
dc.subject | 複合高介電係數介電層 | zh_TW |
dc.subject | 金氧半 | zh_TW |
dc.subject | 可靠度 | zh_TW |
dc.subject | 依時性介電崩潰 | zh_TW |
dc.subject | 缺陷 | zh_TW |
dc.subject | GaN | en_US |
dc.subject | GaAs | en_US |
dc.subject | Stacking High K Dielectrics | en_US |
dc.subject | MOS | en_US |
dc.subject | MIS | en_US |
dc.subject | Reliability | en_US |
dc.subject | TDDB | en_US |
dc.subject | Trap | en_US |
dc.title | 複合高介電係數閘極介電層在三五族半導體中之缺陷特性及其可靠度研究 | zh_TW |
dc.title | A Study of Trap Characteristics and Reliability in Ⅲ-V Compound Semiconductor with Stacking High-k Gate Dielectrics | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子物理系所 | zh_TW |
顯示於類別: | 畢業論文 |