研究半導體和高介電絕緣體之介面以獲得高性能之鍺及三五族金氧半場效電晶體

Abstract

此論文中，我們廣泛地研究各種高介電(high-k)薄膜—包含氮氧化鉿(HfOxNy)、三氧化二鋁(Al2O3)及三氧化二釓(Gd2O3)—在塊材鍺(Ge)及砷化鎵(GaAs)基板上的沉積及元件特性。首先，我們提出兩種表面鈍化方法，氨氣電漿處理及超薄矽批覆，來改善氮氧化鉿濺鍍膜在純鍺基板上；而我們確實看到在經過不管是表面氮化或矽覆蓋製程後，僅少量氧化鍺(GeOx)存在介電層接面、抑制鍺擴散至上層氮氧化鉿以及較少的氧化層電荷捕獲。我們推測這些改善現象是由於減少氧化鍺的揮發及提升高介電層/鍺接面熱穩定性的結果。 我們接續研究原子層沉積(atomic-layer-deposited)三氧化二鋁在純鍺基板上的材料及電特性。發現提升沉積溫度確實改善三氧化二鋁本身的密度及當量化(stoichiometry)；但沉積溫度超過200度將造成三氧化二鋁介電層與氧化鍺接面層的混合，也就是形成氧化鍺鋁中間層(GexAl1-xO intermediate layer)，這將導致白金/三氧化二鋁/鍺(Pt/Al2O3/Ge)電容元件出現較大漏電流及接面缺陷密度(interfacial state density)高達1013 cm-2eV-1以上。另一方面，進一步採用氫氣氮氣混合之熱退火(forming gas annealing)來改善低溫(100度)三氧化二鋁沉積在鍺上的特性，結果發現在靠近能帶中間(midgap)之接面缺陷密度可以下降至約6×1011 cm-2eV-1左右，連遲滯(hysteresis)現象也獲得改善。此外，我們結合電容元件實驗與MEDICI模擬軟體，進一步證實具有高本質載子濃度(intrinsic carrier concentration)的純鍺在透過基板內部缺陷(bulk trap)的產生結合(generation/recombination)或擴散(diffusion)機制，是導致在高頻率下(>103 Hz)會觀察到低頻電容曲線及無電壓相依性之反轉電導(gate-independent inversion conductance)的主因。我們透過電導-電壓(conductance-voltage)特性評估出在低摻雜濃度鍺基板內的缺陷密度約為(2-4)×1015 cm-3左右。阿瑞尼士之基板電導圖(Arrhenius-dependent substrate conductance)也指出在鍺基板內比起在矽基板內有高達104倍的能量損耗(energy loss)，的確反應出具有較快速的次要載子反應速度(minority-carrier response rate)。 論文中，另一研究主題為改善濕式化學清潔(wet-chemical cleaning)及硫化氨處理[(NH4)2S treatment]對於高介電層/砷化鎵之電特性影響。實驗證明，採用氨水鹼性溶液(NH4OH alkaline solution)並搭配80度的硫化氨水溶液[(NH4)2S-H2O]可有效地抑制砷化鎵原生氧化層(GaAs native oxides)及接面附近砷原子(elemental As)的形成，進而改善費米能階釘扎效應(Fermi level pinning effect)對電特性的影響。所製造的三氧化二釓/砷化鎵(Gd2O3/GaAs)電容元件經過最佳化硫化處理後，在電容等效厚度(capacitance-equivalent-thickness)約20埃及閘極電壓在平帶電壓加1伏特[Vg = (VFB+1) V]條件下，可表現出漏電流僅約1.5 × 10-5 A/cm2；已足以匹配他人之前文獻使用超薄矽/鍺鈍化(ultrathin Si/Ge interfacial passivation)之二氧化鉿/砷化鎵電容元件的優越電性表現。而原子層沉積之三氧化二鋁/砷化鎵(ALD-Al2O3/GaAs)電容元件在經過硫化後，也表現出較高的氧化層電容值、較小的頻率離散(frequency dispersion)、微縮的遲滯現象及較低的接面缺陷密度及漏電流成果。且進一步將硫化氨的溶劑(solvent)從水換成丁醇(C4H9OH)將可看到更大幅度的電特性改善，不僅明顯壓抑表面砷原子及氧化砷(AsOx)的量，也形成更多穩定硫鍵結在砷化鎵基板上。另一方面，後續熱退火氣體環境的採用，氧氣及氮氣，對原子層沉積三氧化二鋁/砷化鎵電容元件特性影響，已可透過了解背後熱化學反應機制來理解。此外，我們也注意另一有趣現象，原子層沉積之三氧化二鋁在砷化鎵基板上傾向於高溫(300度)成長，剛好跟它在鍺基板上傾向於低溫(低於200度)成長是相反趨勢。 最後，我們成功地製作出搭配原子層沉積三氧化二鋁高介電層之反轉式(inversion-mode)純鍺P型/N型場效電晶體。純鍺P型電晶體(寬度/長度 = 100 μm/4 μm)呈現載子遷移率峰值(peak mobility)及電流開關比(on-off ratio)分別為225 cm2V–1s–1及大於103；相對地，純鍺N型電晶體(寬度/長度 = 100 μm/9 μm)的載子遷移率峰值及電流開關比分別低於100 cm2V–1s–1及103。而我們認為相對劣等的N型電晶體特性主要跟具有較大的源極/汲極(source/drain)阻值、較嚴重的接面缺陷散射效應以及較低的基板濃度有所關聯性。後續使用300度的氫氣氮氣混合之熱退火不但可以提升驅動電流(on current)、降低能帶缺陷密度以及改善負偏壓熱不穩定性(negative bias temperature instability)可靠度。但提升溫度至400度將會極劇增加N型電晶體的關電流(off current)，這是由於源極/汲極的磷摻雜發生嚴重向外擴散所導致的結果。在此論文中，我們亦調查純鍺接面二極體特性及漏電流路徑，我們得到純鍺P+N及N+P接面二極體整流特性比分別可超過103及104(電壓範圍為±1伏特)，所對應的漏電流為接近10-2 and 10-4 A/cm2。至於漏電流到底是由表面周圍(surface perimeter)或接面面積(junction area)大小所主宰，發現熱製程(摻雜活化或氫氣氮氣混合之熱退火)的使用乃是主要關鍵角色。另一方面，我們也展示具有原子層沉積三氧化二鋁高介電層之空乏式(depletion-mode)砷化鎵N型場效電晶體，在搭配硫化氨-丁醇表面處理後的轉換(transfer)及輸出(output)電特性。在閘極電壓高於臨界電壓4.8伏特以及汲極電壓為4伏特(Vg–Vth = 4.8 V, Vd = 4 V)條件下，汲極電流(Id)約為250 mA/mm。但所萃取出來的電子遷移率峰值僅僅只有336 cm2V-1s-1之多，顯示高介電層/砷化鎵接面品質仍需進一步最佳化。

In this thesis we have extensively investigated the deposition of various high-k dielectric films—including HfOxNy, Al2O3, and Gd2O3—onto the bulk Ge and GaAs substrates and the electrical characteristics of the devices with these developed high-k dielectric films. At first, two surface passivation methods, i.e., the NH3 plasma pretreatment and the ultrathin Si capping, were employed to improve the quality of the sputtered HfOxNy films on the Ge substrates. Not only the severe incorporation of Ge species into the overlying HfOxNy was eliminated, but also the smaller amount of GeOx remained at the dielectric interface and the less oxide trapped charge were observed after undergoing surface nitridation or Si capping processes. These improvements can be attributed to the reduced GeOx volatilization and also enhanced thermal stability of the high-k/Ge interface. We subsequently studied the material and electrical properties of atomic-layer-deposited (ALD) Al2O3 thin films on the Ge substrates. It was found that an increase in the deposition temperature did improve both the density and stoichiometry of the Al2O3 films; nevertheless, temperatures exceeding 200 □C caused the intermixing of top Al2O3 and interfacial GeO2 layers, i.e., the formation of a GexAl1–xO intermediate layer. It led to the consequence of an increasing gate leakage (Jg) and a higher interface state density (Dit, >1013 cm–2eV–1) in the Pt/Al2O3/Ge capacitors. On the other hand, for improving the quality of low-temperature (100 □C) Al2O3 films on the Ge, the forming gas annealing (FGA) at 300 □C was conducted further; the value of the Dit close to midgap was evidently lowered to ca. 6 □ 1011 cm–2eV–1 accompanying with the reduced hysteresis width. In addition, we combined these device experiments with MEDICI simulations and thus validated that a high value of intrinsic carrier concentration (ni) in Ge, via the bulk-trap generation/recombination as well as the diffusion from the bulk substrate, were responsible for the presence of low frequency C-V curves in the kHz regime and the gate-independent inversion conductance. The density of the bulk trap was estimated to be ca. (2–4) □ 1015 cm–3 in the low-doped Ge in terms of their conductance-voltage (G-V) characteristics. The plot of the Arrhenius-dependent substrate conductance (Gsub) also indicated a larger energy loss occurring in Ge than in Si by at least four orders of magnitude, reflecting the fast minority-carrier response rate. We also, afterward, presented the study of the effects of alterant wet-chemical clean and (NH4)2S treatment on the electrical characteristics of high-k/GaAs devices. Through analysis of the surface chemistry, it was evident that employing the NH4OH alkaline solution and then (NH4)2S-H2O passivation at 80 □C effectively suppressed the formation of GaAs native oxides and elemental As close to dielectric interface, thereby abating the “Fermi level (Ef) pinning” effect on the electrical performance. With undergoing the optimized sulfidization processes, the fabricated Gd2O3/GaAs capacitors exhibited the Jg of ca. 1.5 × 10-5 A/cm2 @ Vg = (VFB + 1) V with the capacitance-equivalent-thickness of ca. 20 Å, which is comparable to the earlier study of high-performance HfO2/GaAs system with an ultrathin Si/Ge interfacial passivation. Also, the sulfidized ALD-Al2O3/GaAs capacitors can reveal the resultant higher oxide capacitance, the smaller frequency dispersion, the decreased hysteresis width, the reduced Dit, and the smaller Jg, respectively. Further replacing the (NH4)2S solvent from H2O to C4H9OH indicated a higher electrical improvement, in which an obvious suppression of elemental As and AsOx surface species was found with an increasing sulfur bonds on the GaAs substrates. On the other hand, the influences of post annealing ambient, O2 and N2, adopted in the Al2O3/GaAs capacitor were investigated and we clarified the characteristic differences by identifying the underlying thermochemical mechanisms. In our studies, another interesting feature was noticed that the deposition of the ALD-Al2O3 films on GaAs favored to at the higher temperature, 300 □C, which is opposite to the behavior that those on Ge favored to at low temperatures (<200 □C). Finally, we have successively demonstrated the device characteristics of the inversion-mode Ge p- and n-MOS field-effect-transistors (FETs) with the ALD-Al2O3 gate dielectrics, respectively. The respective peak mobility and on/off ratio was ca. 225 cm2 V–1 s–1 and >103 for Ge p-FET (W/L = 100 μm/4 μm), while these values were less than 100 cm2 V–1 s–1 and ca. 103, respectively, for Ge n-FET (W/L = 100 μm/9 μm). The inferior n-FET device performance can be mainly correlated to the larger source/drain (S/D) contact resistance, the severe Dit scattering, and the lower level of substrate doping. Subsequently performing FGA at 300 °C can enhance the driving on-current, decrease the Dit at the Al2O3–Ge interface, and improve the negative bias temperature instability (NBTI) reliability. A higher FGA temperature of 400 °C led to a dramatic increase in the off-current of the n-FET, arising from the severe out-diffusion of phosphorous dopant from S/D. Herein, the characteristics of Ge junction diodes and their reverse leakage paths were also examined in more details. The magnitudes of the rectifying ratios for the Ge p+n and n+p junctions exceeded three and four orders of magnitude (in the voltage range of ±1 V), respectively, with the values of reverse junction leakage of ca. 10-2 and 10-4 A/cm2, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by (i) the thermal budget during dopant activation and (ii) whether FGA was employed or not. Furthermore, the transfer and output characteristics of the depletion-mode ALD-Al2O3/GaAs n-FET with the (NH4)2S-C4H9OH chemical passivation were also presented. The maximum Id was 250 mA/mm measured at Vg–Vth = 4.8 V, Vd = 4 V. However, the extracted peak electron mobility was only 336 cm2V-1s-1, indicating that optimization of the dielectric/GaAs interface was still required.