晶粒尺寸對多晶矽無接面電晶體之影響

Abstract

無接面(junctionless, JL)電晶體具有製程簡單的優點以外，同時有極佳的短通道效應。因此被認為極具有潛力作為取代傳統式(inversion mode, IM) MOSFET 的電晶體。在本研究當中，利用不同初始的非晶矽厚度，搭配固相結晶法產生不同晶粒大小之多晶矽通道層，並將通道層薄化至相同厚度，探討晶粒大小對多晶矽無接面場效電晶體的影響，並 與傳統多晶矽電晶體做比較。首先，我們提出利用超薄體(ultra-thin body，UTB)結構提升閘極對通道的控制能力以抑制漏電並同時改善次臨界擺幅(subthreshold slope，S.S.)與短通道效應控制能力。在此，同時討論 UTB-IM 與 UTB-JL TFT 在不同晶粒尺寸下對電性的差異，當晶粒尺寸之直徑由 80nm 升至 450nm 時，UTB-IM TFT 的開啟電流(I on )由 5.41μA 升至 13.9μA; UTB-JL TFT 則由 4.71μA 升至 12.7μA，同時，UTB-IM TFT 的關閉電流(I min )由 9.72pA 降至0.18pA; UTB-JL TFT 則由 9.72pA 降至 0.38pA，因此，隨著晶粒尺寸的上升，UTB-IM TFT 以及 UTB-JL TFT 的開關電流比都能夠達到約 10 7 。次臨界擺幅以及汲極引致能障下降(DIBL)亦隨著晶粒尺寸上升而能夠得到改善。另外，由於在製作超薄體結構的過程中，電漿乾式蝕刻法以及離子佈值(ion implantation)將造成額外的缺陷，因此我們利用氨氣電漿處理，實驗結果發現經過電漿處理後，UTB-IM TFT 以及 UTB-JL TFT 的開啟電 流，次臨界擺幅以及 DIBL 都能夠獲得改善並且提升。此外，為了抑制晶粒邊界及多晶矽通道層與閘極介電層介面處的缺陷，我們進一步 討論奈米線(nanowire, NW)立體結構下對於 IM 以及 JL poly-Si TFT 之影響。實驗結果可以發現，由於閘極對於通道的控制能力在奈米線結構下得到提升，因此，NW-IM TFT 的次臨界擺幅可以達到 112mV/dec 而 NW-JL TFT 更是改善至 90mV/dec。在開啟電流I on的表現上，NW-IM TFT 的開啟電流為 11.3μA 而 NW-JL TFT 則是 11μA;另外，關閉電流I min 則分別為 0.59pA 以及 0.29pA，所以，NW-JL TFT 的開關電流比(3.79 × 10 7 )約為 NW-IM TFT (1.9 × 10 7 )的兩倍。 最後，綜合以上研究結果: (一) 不同晶粒大小之超薄體多晶矽無接面薄膜電晶體(UTB poly-Si JL TFT)，相對於超薄體多晶矽傳統是薄膜電晶體(UTB poly-Si IM TFT)，具有更陡峭的次臨界擺幅、較低的關閉電流以及極高的開啟電流。 (二) 奈米線結構大幅度的提升多晶矽無接面薄膜電晶體在電性上的表現，次臨界擺幅達到 90mV/dec、極高的開啟電流 11μA 以及關閉電流 0.29pA，這樣的表現運用在功率高效能及三維積體電路占有極高的潛力。

Junctionless transistors are considered as promising architecture to take place of conventional metal-oxide-silicon field effect transistors (MOSFETs) for continuously scaling down due to simple fabrication and better short-channel effect (SCE) immunity. In this research, different initial thickness of α-Si film would be crystallized by solid phase crystallization (SPC) to yield different grain size of poly-Si channel. Then, etching back process made poly-Si channel achieve the same channel thickness with different grain size. As a result, we will discuss the effect of grain size on polycrystalline silicon (poly-Si) junctionless TFTs. First of all, ultra-thin body (UTB) structure which can enhance the gate to channel coupling, suppress leakage current, and improve subthreshold swing (S.S.) is proposed to be utilized. Then, electric transfer characteristics of inversion mode (IM) and junctionless (JL) TFTs with different grain size are discussed. On current (I on ) of UTB-IM TFT improves from 5.41μA to 13.9μA, and of UTB-JL TFT enhances from 4.71μA to 12.7μA. Furthermore, leakage current (I min ) of UTB-IM TFT decreases from 9.72pA to 0.18pA; on the other hand, I min of UTB-JL TFT reduces from 9.72pA to 0.38pA. The on/off current ratio of both devices shows about 10 7 referring to better switching capability. S.S. and drain induced barrier lowering (DIBL) are also refined by larger grain size. In addition, defects in grain boundaries (GBs), interface between poly-Si channel and gate oxide, damage from etching back and ion implantation are passivated by NH 3 plasma treatment. As a result, I on , S.S., and DIBL can be further improved by NH 3 plasma treatment. Then, to suppress the side effect from defects in GBs and interface between surface of channel and gate oxide, grain size effect on nanowire (NW) poly-Si TFTs will be ceaselessly discussed. It demonstrates that S.S. of NW-IM TFT achieves to 112mV/dec, and of NW-JL TFT attains 90mV/dec owing to better gate to channel coupling by tri-gated structure. Additionally, I on (11.3μA), and I min (0.59pA) are displayed by NW-IM TFT and I on (11μA), and I min (0.29pA) are exhibited by NW-JL TFT. Hence, NW-JL TFT demonstrates 2 fold higher I on /I min current ratio than of NW-IM TFT. Finally, UTB poly-Si JL TFT with large grain size by SPC shows a steeper S.S., higher I on and lower I min than UTB poly-Si IM TFT. Additionally, NW poly-Si JL TFT with large grain size shows ultra-steep S.S. of 90mV/dec, high-ranking I on of 11μA, and low I min of 0.29pA. The performance of NW poly-Si JL TFT with large grain size can be highly used in high performance and three dimensional integrated circuits.