标题: | 晶粒尺寸对多晶矽无接面电晶体之影响 Effect of Grain Size on Polycrystalline-Silicon Junctionless Thin-Film Transistors |
作者: | 张壬泓 赵天生 Chang, Jen-Hong Chao, Tien-Sheng 电子物理系所 |
关键字: | 多晶矽;无接面电晶体;超薄体;奈米线;电浆处理;poly silicon;junctionless transistor;ultra thin body;nano wire;plasma treatment |
公开日期: | 2017 |
摘要: | 无接面(junctionless, JL)电晶体具有制程简单的优点以外,同时有极佳的短通道效应。因此被认为极具有潜力作为取代传统式(inversion mode, IM) MOSFET 的电晶体。在本研究当中,利用不同初始的非晶矽厚度,搭配固相结晶法产生不同晶粒大小之多晶矽通道层,并将通道层薄化至相同厚度,探讨晶粒大小对多晶矽无接面场效电晶体的影响,并 与传统多晶矽电晶体做比较。首先,我们提出利用超薄体(ultra-thin body,UTB)结构提升闸极对通道的控制能力以抑制漏电并同时改善次临界摆幅(subthreshold slope,S.S.)与短通道效应控制能力。在此,同时讨论 UTB-IM 与 UTB-JL TFT 在不同晶粒尺寸下对电性的差异,当晶粒尺寸之直径由 80nm 升至 450nm 时,UTB-IM TFT 的开启电流(I on )由 5.41μA 升至 13.9μA; UTB-JL TFT 则由 4.71μA 升至 12.7μA,同时,UTB-IM TFT 的关闭电流(I min )由 9.72pA 降至0.18pA; UTB-JL TFT 则由 9.72pA 降至 0.38pA,因此,随着晶粒尺寸的上升,UTB-IM TFT 以及 UTB-JL TFT 的开关电流比都能够达到约 10 7 。次临界摆幅以及汲极引致能障下降(DIBL)亦随着晶粒尺寸上升而能够得到改善。另外,由于在制作超薄体结构的过程中,电浆干式蚀刻法以及离子布值(ion implantation)将造成额外的缺陷,因此我们利用氨气电浆处理,实验结果发现经过电浆处理后,UTB-IM TFT 以及 UTB-JL TFT 的开启电 流,次临界摆幅以及 DIBL 都能够获得改善并且提升。此外,为了抑制晶粒边界及多晶矽通道层与闸极介电层介面处的缺陷,我们进一步 讨论奈米线(nanowire, NW)立体结构下对于 IM 以及 JL poly-Si TFT 之影响。实验结果可以发现,由于闸极对于通道的控制能力在奈米线结构下得到提升,因此,NW-IM TFT 的次临界摆幅可以达到 112mV/dec 而 NW-JL TFT 更是改善至 90mV/dec。在开启电流I on的表现上,NW-IM TFT 的开启电流为 11.3μA 而 NW-JL TFT 则是 11μA;另外,关闭电流I min 则分别为 0.59pA 以及 0.29pA,所以,NW-JL TFT 的开关电流比(3.79 × 10 7 )约为 NW-IM TFT (1.9 × 10 7 )的两倍。 最后,综合以上研究结果: (一) 不同晶粒大小之超薄体多晶矽无接面薄膜电晶体(UTB poly-Si JL TFT),相对于超薄体多晶矽传统是薄膜电晶体(UTB poly-Si IM TFT),具有更陡峭的次临界摆幅、较低的关闭电流以及极高的开启电流。 (二) 奈米线结构大幅度的提升多晶矽无接面薄膜电晶体在电性上的表现,次临界摆幅达到 90mV/dec、极高的开启电流 11μA 以及关闭电流 0.29pA,这样的表现运用在功率高效能及三维积体电路占有极高的潜力。 Junctionless transistors are considered as promising architecture to take place of conventional metal-oxide-silicon field effect transistors (MOSFETs) for continuously scaling down due to simple fabrication and better short-channel effect (SCE) immunity. In this research, different initial thickness of α-Si film would be crystallized by solid phase crystallization (SPC) to yield different grain size of poly-Si channel. Then, etching back process made poly-Si channel achieve the same channel thickness with different grain size. As a result, we will discuss the effect of grain size on polycrystalline silicon (poly-Si) junctionless TFTs. First of all, ultra-thin body (UTB) structure which can enhance the gate to channel coupling, suppress leakage current, and improve subthreshold swing (S.S.) is proposed to be utilized. Then, electric transfer characteristics of inversion mode (IM) and junctionless (JL) TFTs with different grain size are discussed. On current (I on ) of UTB-IM TFT improves from 5.41μA to 13.9μA, and of UTB-JL TFT enhances from 4.71μA to 12.7μA. Furthermore, leakage current (I min ) of UTB-IM TFT decreases from 9.72pA to 0.18pA; on the other hand, I min of UTB-JL TFT reduces from 9.72pA to 0.38pA. The on/off current ratio of both devices shows about 10 7 referring to better switching capability. S.S. and drain induced barrier lowering (DIBL) are also refined by larger grain size. In addition, defects in grain boundaries (GBs), interface between poly-Si channel and gate oxide, damage from etching back and ion implantation are passivated by NH 3 plasma treatment. As a result, I on , S.S., and DIBL can be further improved by NH 3 plasma treatment. Then, to suppress the side effect from defects in GBs and interface between surface of channel and gate oxide, grain size effect on nanowire (NW) poly-Si TFTs will be ceaselessly discussed. It demonstrates that S.S. of NW-IM TFT achieves to 112mV/dec, and of NW-JL TFT attains 90mV/dec owing to better gate to channel coupling by tri-gated structure. Additionally, I on (11.3μA), and I min (0.59pA) are displayed by NW-IM TFT and I on (11μA), and I min (0.29pA) are exhibited by NW-JL TFT. Hence, NW-JL TFT demonstrates 2 fold higher I on /I min current ratio than of NW-IM TFT. Finally, UTB poly-Si JL TFT with large grain size by SPC shows a steeper S.S., higher I on and lower I min than UTB poly-Si IM TFT. Additionally, NW poly-Si JL TFT with large grain size shows ultra-steep S.S. of 90mV/dec, high-ranking I on of 11μA, and low I min of 0.29pA. The performance of NW poly-Si JL TFT with large grain size can be highly used in high performance and three dimensional integrated circuits. |
URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070352014 http://hdl.handle.net/11536/142218 |
显示于类别: | Thesis |