利用準分子雷射結晶製備具控制晶界位置之鍺薄膜電晶體之研究

Abstract

鍺(Germanium, Ge)擁有比矽高的載子遷移率，且其元件製程與矽基元件相容，因此被視為最具吸引力之下世代通道材料之一。而鍺基元件製程溫度較矽基元件為低，故鍺基元件具備積層型堆疊(Monolithic stacking)三維積體電路應用潛力。運用準分子雷射結晶可製作出具有大小達1微米之大晶粒的高品質多晶鍺薄膜，並有效降低因缺陷產生的電洞濃度。然而藉由傳統準分子雷射結晶製備的p型通道多晶鍺薄膜電晶體，因鍺薄膜各處晶粒大小不一致，且晶界(Grain boundary, GB)仍任意分布於通道區域，而導致較低的載子遷移率及較差的元件對元件均勻性。本篇論文中我們提出利用具凹陷形通道(Recessed-channel, RC)結構之鍺薄膜，藉由準分子雷射結晶法實現具位置控制晶界(Location-controlled grain boundary, LCGB)之高品質鍺薄膜，並藉此製作高性能p型通道鍺薄膜電晶體之元件。 本文首先探討具備不同凹陷形通道結構之鍺薄膜與不同的二氧化矽覆蓋層厚度對鍺薄膜雷射結晶之影響。結果顯示，採用具備厚區(Thick region)厚度240奈米與凹陷區(Recessed region)厚度150奈米之凹陷形通道鍺薄膜，再搭配厚度300奈米的二氧化矽覆蓋層，經雷射退火後可成功於凹陷區得到具位置控制晶界之大晶粒。進一步研究此種凹陷形通道受不同能量密度之雷射退火之結果，得對於厚區長度3微米與凹陷區長度2微米的凹陷形通道鍺薄膜，可於施打能量密度為340 mJ/cm2以上之雷射退火後，成功在凹陷區獲得具位置控制晶界之大晶粒－亦即在凹陷區內形成長形（Longitudinal）大晶粒，並於中央處形成單一垂直晶界(Perpendicular GB)。這是因為此時凹陷區為全熔融(Complete-melted)，而厚區為部分熔融(Partial-melted)，使到鍺薄膜自凹陷區朝相鄰厚區產生水平溫度梯度，進一步以厚區內未熔融處為晶種，向凹陷區進行水平晶粒成長，最終自兩邊厚區成長之水平晶粒於凹陷區中央相遇而形成垂直晶界。本文亦有探討厚區長度和凹陷區長度對於鍺薄膜雷射結晶之影響。結果顯示，對於厚區長度3微米的凹陷形通道鍺薄膜，於凹陷區長度為3微米以下可成功獲得具位置控制晶界之大晶粒分布；另一方面，對於凹陷區長度2微米之凹陷形通道鍺薄膜，於厚區長度1.2微米以上可成功獲得具位置控制晶界之大晶粒。 本文接著採用厚區長度3微米與凹陷區長度2微米的凹陷形通道鍺薄膜製備p型通道鍺薄膜電晶體，製作過程中除對薄膜進行雷射退火外，亦利用磷離子劑量為1.2 × 1014 cm-2之反向摻雜使鍺薄膜轉變為n型。結果顯示，經過400 mJ/cm2之雷射退火製備出之通道長度0.5微米而有效寬度0.8微米之鍺薄膜電晶體，其場效電洞遷移率可達494 cm2 V-1 s-1，而開關電流比可達3.7 × 103。比較凹陷形通道鍺薄膜電晶體(RC Ge TFT)與傳統雷射結晶得之鍺薄膜電晶體之電性，可得不論是電洞遷移率還是開關電流比，凹陷形通道鍺薄膜電晶體之表現皆優於與傳統鍺薄膜電晶體。也同時進一步比較通道在凹陷形通道鍺不同位置上之薄膜電晶體電性的影響，發現將元件通道區域設計在可避開垂直晶界之位置時，能獲得比元件通道內含垂直晶界者為佳之電洞遷移率與開關電流比。 綜前所述，採用具凹陷形通道結構之鍺薄膜搭配準分子雷射結晶與反向摻雜，可製得具備高電洞遷移率與高開關電流比之高效能p型通道鍺薄膜電晶體，對於未來在下世代電晶體與積層型三維元件整合應用等相關領域具備極大發展潛力。

Germanium (Ge) has the advantages of its much higher carrier mobility than silicon (Si) and its device fabrication process compatible with Si-based devices. Therefore, Ge has been considered as one of the most attractive next-generation channel materials. Moreover, the process temperature of Ge-based devices is typically lower than Si-based ones. Thus, Ge-based devices have a great potential for the monolithic stacking applications in three-dimensional integrated circuits (3-D ICs) fields. This fact makes the Ge-on-insulator (GOI) devices attract wide attention. High-quality polycrystalline-germanium (Poly-Ge) thin films with large grains as large as 1 μm as well as the reduced defect-generated hole concentrations have been achieved by using the excimer laser crystallization (ELC) method. It makes the p-channel poly-Ge thin-film transistors (TFTs) fabricated by ELC attain a good hole mobility. However, the ELC Ge TFTs still have a lower carrier mobility and poor device-to-device uniformity as compared to the GOI devices. This can be attributed to the variations in grain sizes and the random distribution of grain boundaries (GBs) in the channel region. In this thesis, we proposed a method to attain high-quality Ge thin films with the location-controlled grain boundary (LCGB) structure via ELC by to treat the Ge recessed-channel (RC) structure. At First, this thesis demonstrates the effects of various RC structures and the SiO2 capping layer thickness on the crystallization of RC Ge thin films. The results revealed that the large grain with the LCGB structure could be successfully achieved in the recessed region of RC Ge thin films with a thick-region Ge thickness of 240 nm, a recessed-region Ge thickness of 150 nm, and a SiO2-capping-layer thickness of 300 nm, respectively. Then, we discussed the effect of the laser energy density (E) on the laser crystallization of this kind of the RC Ge thin films. The LCGB structure, involving large longitudinal grains with a single perpendicular GB in the middle, could be successfully formed in the recessed region of RC Ge thin films with a thick-region length (LTK) of 3 μm and a recessed-region length (LRC) of 2 μm via ELC at E ≥ 340 mJ/cm2. This is because the recessed region is complete-melted and the thick region is partial-melted during ELC, leading to the lateral thermal gradient from the recessed region to the adjacent thick regions. Thus, the large grains grow laterally from the un-molten solid seeds in the thick region toward the recessed region. At last, the large grains growing laterally from both sides impinge at the middle of the recessed region, resulting in the formation of a single perpendicular GB. Subsequently, we discussed the effects of LTK and LRC on the laser crystallization of RC Ge thin films. The LCGB structure could be successfully formed as LRC ≤ 3 μm for the RC Ge thin films with LTK = 3 μm. The LCGB structure could be also attained as LTK ≥ 1.2 μm for the RC Ge thin films with LRC = 2 μm. This thesis then reports the demonstration of the p-channel Ge TFTs by using the RC Ge thin films with LTK = 3 μm and LRC = 2 μm. During the TFT fabrication process, besides the Ge ELC, a counter-doping (CD) process with the phosphorus ion dose of 1.2 × 1014 cm-2 was employed in order to convert the Ge thin films to the n-type films. The results revealed that the RC Ge TFTs with a channel length of 0.5 μm and an effective channel width of 0.8 μm fabricated via ELC at E = 400 mJ/cm2 attained the field-effect hole mobility (μFE) of 494 cm2 V-1 s-1 and the on/off current ratio (Ion/Ioff) of 3.7 × 103. Moreover, both the hole mobility and the Ion/Ioff of RC Ge TFTs were better as compared with poly-Ge TFTs fabricated by conventional ELC. We also compared the electrical characteristics of RC Ge TFTs with various channel positions. The results show that the RC Ge TFTs without the perpendicular GB in the channel region exhibited higher hole mobility and higher Ion/Ioff than those with the perpendicular GB. In summary, high-performance p-channel Ge TFTs with a high hole mobility and a high Ion/Ioff could be successfully achieved by employed the Ge thin films with the RC structure fabricated via ELC and CD. These TFTs show a great potential for the future applications in the next generation transistors and monolithic 3-D stacking.