標題: 自組裝成長矽奈米線及其電性量測
Bottom-up Growth and the Electrical Property of Si Nanowires
作者: 鄒勝傑
周苡嘉
Tzou, Sheng-Jie
Chou, Yi-Chia
電子物理系所
關鍵字: 矽奈米線;自組裝成長;電性量測;氣液固成長機制;Si nanowire;Bottom-up;Electrical property;Vapor-liquid-solid growth mechanism
公開日期: 2017
摘要: 本實驗在超高真空化學氣相沉積(Ultra-high vacuum chemical vapor deposition, UHV-CVD)系統中,以金屬催化的方式成長矽奈米線於矽基板上。研究在UHV-CVD中調變不同的成長參數,對於矽奈米線的表面形貌、成長速率所造成的影響,並探討其背後物理機制,此外,也量測奈米線的電性表現。 在成長參數影響奈米線表面形貌的研究中,發現成長溫度對於奈米線的半徑與表面形貌有相當顯著的影響,金屬催化劑的多寡影響奈米線在基板上的分布密度,另外,我們也發現要成長表面形貌優異的奈米線,除了精準的掌握成長溫度、良好的成長環境,基板的潔淨度更是扮演著相當重要的角色。成長速率則與前驅氣體的壓力(Precursor gas pressure)、成長溫度,有相當重要的關聯性。 電性量測方面,我們利用電子束微影(E-beam lithography)的方式,將奈米線與定位基板上的大電極連接,量測矽與氮化鎵奈米線的I-V curve。為了能夠精確的得到奈米線電阻率,我們利用內插法的方式算出奈米線的接觸電阻與奈米線電阻隨長度變化的關係,矽奈米線的電阻率為85("om×m" ),試著與其他研究團隊利用分子束磊晶(Molecular beam epitaxy, MBE)成長的矽奈米線進行比較,發現利用這兩種方式成長出來的矽奈米線電阻率是一致。 為了未來能與GaN奈米線進行整合,形成Si/GaN的異質結構,我們討論如何藉由兩種不同種類的金屬形成合金,利用金屬催化的方式製作交界分明的異質接面,此外,也對於GaN奈米線進行電性量測,同樣與其他研究團隊利用MBE成長出來的GaN奈米線進行比較發現使用氫化物氣相磊晶(Hydride vapor phase epitaxy, HVPE)成長的GaN奈米線電阻率小了許多,接著我們將GaN奈米線進行低溫螢光光譜(Photoluminescence, PL)檢測,發現有許多非本質發光帶,我們認為這些缺陷是造成GaN奈米線電阻率變低的原因。
In our research, we use the metal-catalyst growth method to grow Si nanowires on Si substrate in ultra-high vacuum chemical vapor deposition (UHV-CVD). We investigate the influence of different growth parameters on morphology and growth rate of Si nanowires in UHV-CVD and discuss the mechanism. Besides, we also measure electrical properties of Si nanowires. We find that growth the temperature significantly influence on morphology and the growth rate, thickness of metal catalyst is related to the number of nanowires on substrate. In addition to appropriate growth temperature, we also observe that substrate cleanliness is another critical point for excellent morphology of nanowires. In the other hand, growth temperature and precursor gas pressure are closely related to growth rate. For the electrical property measurement, we use e-beam lithography method to connect nanowire with the pad and measure I-V curve of the Si NWs and GaN NWs. To remove contact resistance, we adopt interpolation method which is suitable for high resistance material. The resistivity of Si nanowire is 85 (ohm"×" m). The resistivity of Si nanowire in this thesis is similar to that grown by MBE in literature. For the purpose of forming Si/GaN heterostructure, we discuss how to form clear interface in the heterostructure by alloy-catalyst growth method. Besides, we measure the resistivity of GaN NWs. The value is lower than the resistivity of GaN grown by MBE. By using the low temperature photoluminescence analysis, we confirm the multiple defects in the GaN nanowire, which result in lower resistivity.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070452009
http://hdl.handle.net/11536/142383
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