低複雜度多倍平行之2^k基底串列交換架構及混合基底2^α 3^β 5^γ點數快速傅立葉轉換處理器架構之設計

Abstract

在本論文中，我們提出二種快速傅立葉轉換處理器設計。首先，為了提高串列交換架構的吞吐率，提出一個多倍平行之基底-2串列交換架構設計，亦稱為多重路徑串列交換架構。為了降低硬體成本，將FFT演算法從基底-2延伸至高基底- ，且改善傳統基底-2^4演算法，提出一個改良式基底- 串列交換處理單元。利用改良式基底-2^4處理單元，設計一個四倍平行之128點基底-2^4串列交換架構。且針對最新IEEE 802.11ax標準，提出一個可提供1.2G sample/s的低複雜度八倍平行之混合基底2048點快速傅立葉轉換處理器，使用TSMC 90nm製程技術，合成面積為0.746mm^2 ，在工作頻率150MHz下，功率消耗為37.25mW 。第二個設計是針對LTE上行系統使用的單載波分頻多重接取(SC-FDMA)技術，其快速傅立葉轉換點數包含2、3、5因子，因此本文提出一個二倍平行之共享式3點或5點快速傅立葉轉換處理單元，並將此處理單元應用在多重路徑延遲交換架構，提出一個適用於多平行度之混合基底 點快速傅立葉轉換處理器架構設計方案，此架構具有低延遲、高吞吐率優點。

This work presents two different FFT processor designs. First, to enhance the throughput of the original serial commutator (SC) pipelined architecture, we propose parallel radix-2 serial commutator designs, called multi-path serial commutator (MSC). First, in order to achieve lower hardware complexity, we extend our previous radix-2 architecture to radix- architecture. We improve traditional radix-2^4 algorithm and design an area-efficient modified radix-2^4 processing element used in SC architecture. Next, we design a 4-parallel radix-2^4 128-point SC FFT processor by using the above mentioned processing element. In addition, we proposed a low-complexity processor for 8-parallel mixed-radix 2048-point FFT with throughput of 1.2G sample/s for the newest IEEE 802.11ax WLAN standard. The proposed design is implemented with TSMC 90 nm process technology. The area and power consumption of the synthesis results are respectively 0.746mm^2 and 37.25mW under 150MHZ working frequency. In the second design, a shared 2-parallel 3-point and 5-point FFT processing element is proposed, for the consideration of FFT sizes required in LTE/LTE-A system which include 2, 3 and 5 factors. By applying the prime factor PE to multi-path delay commutator architecture, we propose a parallel mixed-radix -point FFT processor design. This architecture has advantages of low latency and high throughput.