完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chiou, JC | en_US |
dc.contributor.author | Wang, HI | en_US |
dc.contributor.author | Chen, MC | en_US |
dc.date.accessioned | 2014-12-08T15:02:48Z | - |
dc.date.available | 2014-12-08T15:02:48Z | - |
dc.date.issued | 1996-03-01 | en_US |
dc.identifier.issn | 0013-4651 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/1424 | - |
dc.description.abstract | The impact of Cu on the dielectric SiO2 layer was studied using a Cu/SiO2/Si metal oxide semiconductor capacitor and rapid thermal annealing (RTA) treatment. With the RTA treatment, no chemical reaction was observed up to 900 degrees C; however, dielectric degradation occurred following RTA at 300 degrees C for 60 s and became worse with the increase of annealing temperature. The interface-trap density at the SiO2/Si interface also increased from 5 x 10(10) to 5 x 10(13) eV(-1) cm(-2) after 800 degrees C RTA treatment. The RTA anneal introduced a large number of positive Cu ions into the dielectric SiO2 layer. Under bias-temperature stress, Cu ions drift quickly in the SiO2 layer and may drift across the SiO2/Si interface and enter the Si substrate. With the use of 1200 Angstrom thick TiN and TiW barrier layers, respectively, the dielectric strength of the Cu/(barrier)/SiO2/Si structures was able to remain stable up to 500 and 600 degrees C. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Dielectric degradation of Cu/SiO2/Si structure during thermal annealing | en_US |
dc.type | Article | en_US |
dc.identifier.journal | JOURNAL OF THE ELECTROCHEMICAL SOCIETY | en_US |
dc.citation.volume | 143 | en_US |
dc.citation.issue | 3 | en_US |
dc.citation.spage | 990 | en_US |
dc.citation.epage | 994 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1996UC20300043 | - |
dc.citation.woscount | 21 | - |
顯示於類別: | 期刊論文 |