適用於暫存器轉移層設計除錯之以機器學習為基礎的錯誤分流技術

Abstract

當電路的設計越來越複雜，在設計的流程中，驗證和除錯在暫存器轉移層已經成為主要的痛點。如果在設計的過程中有任何的功能缺失，在進行回歸測試時，多樣性的錯誤將會一一呈現。為了能夠更有效率的診斷和修正這些錯誤，將這些錯誤做好的分類和排序將會是必要的。因此，本論文提出了一個以機器學習為基礎的錯誤分流技術。此引擎的第一步將會收集這些在回歸測試失敗的測試案例，並且藉由以SAT為基礎的除錯技術找尋可以錯誤的來源；接著，藉由數據加權方案定義，透過基於特徵的矩陣來表示這些錯誤，最後，應用先進的基於機器學習的聚類演算法，獲得相對應群聚的錯誤分流，並且提供相對應的可信度排序。實驗結果顯示，這個分流引擎在整體的表現有90%的準確度能夠得到高品質的錯誤分流，並且得到精準的可信度排序。

Verification and debugging have become the major pain-point in Register Transfer Level (RTL) design as design size and complexity increase. If there is a functional bug in RTL design, numerous and diverse failures would be exposed in the regression test. To diagnose and fix design errors more efficiently, categorizing and prioritizing these failures is necessary. In this work, a machine learning based failure binning engine is proposed. First, the engine will collect failures from testbench simulation, and then try to explore suspect elements by SAT-based debugging technique. Next, a suspect data weighting scheme is defined to represent failures by a feature-based matrix. Finally, an advanced machine learning based clustering algorithm is applied to obtain the failure bins with respective confidence rank. Experimental results show the failure binning engine demonstrates an overall accuracy of 90% that obtains high-quality bins with the accurate confidence ranking.