增量式佈局及邏輯閘尺寸調整以降低靜態功率消耗

Abstract

隨著半導體製程越來越小，功率消耗的問題由於漏電流的影響變得不可忽略。在電路最佳化的時候，功率消耗與延遲是一個權衡的關係，本篇研究提出了一個結合了增量式佈局及邏輯閘尺寸調整的流程以降低靜態功率消耗。在本篇實驗中，我們採用了以拉格朗日鬆弛技術為核心的邏輯閘尺寸調整引擎以及商業工具SoC Encounter，而增量式佈局的部分使用貪婪演算法來完成。我們自己創造了些許電路並使用近幾年的ISPD競賽的測試資料來驗證我們的演算法。在自製的電路中，我們做了些實驗驗證本篇所提的理論，另外我們分析了結果不如預期的測試用例並整理其原因。大多數關於佈局的研究都是著重於時態最佳化的部分，而我們的研究提供了另一個的面向(降低功率消耗)的討論。

As the technology keeps scaling down, the importance of power dissipation becomes signifi-cant due to the increasing leakage. Since power and timing are tradeoffs during optimization, in this research, we propose a flow combing incremental placement and gate sizing to alter the power-timing curve and further achieve leakage power reduction. A LR (Lagrangian Re-laxation) based gate sizing engine and the commercial tool SoC Encounter are used in this approach. We apply a greedy heuristic algorithm for the incremental detailed placement in our framework. The test benches are several self-made schematics and the hybrid ISPD con-test benchmarks. Our theory is verified by several experiments on manual test cases. We in-vestigate the results that are not as good as we expected and analyze the reasons. Since most of researches in placement focus on timing optimization, this approach brings a different point of view on incremental placement.