具有突發模式的高效率和快速暫態反應之數位低壓差穩壓器對應於DC-DC開關轉換器的節能模式

Abstract

單晶片系統中的電源管理技術包括用於高轉換率的高效率DC-DC開關穩壓器和用於不同功能塊後置調節的數位線性低壓差穩壓器。開關穩壓器中的高效省電模式有效地提高了輕載效率，例如，突發模式，跳過模式，脈衝頻率模式。不幸的是，次級數位線性穩壓器雖然已經使用最近的技術，卻從數位線性穩壓器中異常消耗更多的功率來抑制開關穩壓器的電壓漣波。電源管理的總體輕載效率嚴重下降。採用桶形移位器控制的數位線性穩壓器由於限制循環振盪而導致大的電壓波動，並且具有降低功耗的凍結模式的數位線性穩壓器會自動從開關穩壓器中暴露於較大的電壓波動。傳輸的大電壓波紋導致數位線性穩壓器經常在正常模式和凍結模式之間切換並消耗大量功率。在省電模式下，顯而易見的缺點是將產生大的開關穩壓器的輸出漣波電壓，最先進的數位線性穩壓器設計引起額外的開關損耗，並引起大的輸出漣波電壓。因此，本文提出了使用突發模式技術的數位線性穩壓器來減少輸出漣波電壓，並提高與開關穩壓器中節能模式相對應的整體輕載效率。所提出的非線性開關控制技術減少了開/關電源開關的數量，並改變了對應於開關穩壓器的頻率。此外，當數位線性穩壓器離開突發模式時，所提出的瞬態增強技術提高了瞬態性能。

Integrated power management (PM) in the system-on-a-chip (SoC) includes high efficiency DC-DC switching regulator (SWR) for high conversion ratio and multiple cascaded digital low dropout (DLDO) regulators for post regulation in different functional blocks. Efficient power saving modes in the SWRs improve the light-load efficiency effectively, e.g. burst mode, skip mode, pulse frequency mode (PFM), and diode emulation mode (DEM) in the constant on-time (COT). Unfortunately, the cascaded DLDO abnormally consumes more power to suppress large voltage ripple ΔVSWR from the SWR even using the recent DLDO techniques. Overall light-load efficiency of the PM seriously decreases. DLDO with a barrel-shifter-based control induces large voltage ripples due to the limiting cycle oscillation (LCO) effect. DLDO with a freeze mode for power reduction exposures itself to large voltage ripples from the SWRs (in power saving modes). The transmitted large voltage ripples result in the DLDO frequently switching between the normal and freeze modes and thereby consuming much power. In power saving modes, the obvious disadvantage include state-of-the-art DLDO designs cause extra switching loss and induce large output voltage ripple ΔVOUT from the large ΔVSWR. Thus, this thesis proposes the DLDO with the burst mode technique (BMT) to reduce the ΔVOUT and enhance the overall light-load efficiency corresponding to the power saving modes in SWRs. The proposed non-linear switch control (NLSC) technique reduces both the number of on/off power switches and varies the switching frequency corresponding to the ΔVSWR. Moreover, the proposed transient enhance (TE) technique improves transient performance when the DLDO leaves the burst mode.