A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters

doi:10.1109/TPEL.2019.2939415

標題:	A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
作者:	Lin, Jian-He Yang, Shang-Hsien Muniandi, Balakumar Ma, Yu-Sheng Huang, Chia-Ming Chen, Ke-Horng Lin, Ying-Hsi Lin, Shian-Ru Tsai, Tsung-Yen 電機工程學系 Department of Electrical and Computer Engineering
關鍵字:	Regulators;Switches;Voltage control;Transient analysis;Switching frequency;Transient response;Digital low-dropout regulator (DLDO);nonlinear switch control (NLSC) technique;power-saving mode;variable switching frequency control
公開日期:	1-Apr-2020
摘要:	The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 A and reduces the switching power loss through variable switching frequency control. With a load step of 1-20mA, the transient response time is 1.3 s and the peak current efficiency is 99.8 at heavy loads.
URI:	http://dx.doi.org/10.1109/TPEL.2019.2939415 http://hdl.handle.net/11536/153560
ISSN:	0885-8993
DOI:	10.1109/TPEL.2019.2939415
期刊:	IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume:	35
Issue:	4
起始頁:	3997
結束頁:	4008
Appears in Collections:	Articles