應用於第五代行動通訊36-40 GHz之低雜訊放大器設計

Abstract

本篇論文提出一應用於毫米波段接收器中的低雜訊放大器，其操作頻率為36~40 GHz，可應用於第五代行動通訊，此低雜訊放大器之主要特色為設計時阻抗匹配點之選擇兼顧雜訊及輸出功率之表現。 論文會先對低雜訊放大器的設計作探討，並利用WIN 0.15μm pHEMT製程去實現一個以二級串接架構設計之低雜訊放大器，低雜訊放大器其主要功能在於放大訊號並抑制雜訊，以維持良好之訊雜比(SNR，Signal to Noise Ratio)。此外，在滿足低雜訊的要求外，其線性度之表現亦是另一個重點，藉由WIN 0.15μm pHEMT製程高線性度的特性，實現同時具有良好雜訊表現，並兼顧線性度表現之低雜訊放大器。 本篇論文所實作之低雜訊放大器，操作頻率為38 GHz，最低雜訊指數為2.88 dB，此設計的增益為18.9 dB，輸出1dB壓縮點為7.92dBm，輸出三階截止點為16dBm，消耗功率為152 mW，晶片尺寸為2x1mm2。

A 36~40 GHz two stage LNA design for fifth generation cellular wireless systems is proposed in this thesis. The main feature of this LNA is the choice of impedance matching point to taking the performance of noise and output power into account. Firstly, the basic LNA design is discussed, and a two stage low noise amplifier is fabricated by WIN 0.15μm pHEMT. The main function of the LNA is to amplify the signal received by antenna and suppress the noise to maintain a good SNR(Signal-to-Noise Ratio). In addition, the performance of linearity is another point. Thus, a LNA with good noise performance and good linearity performance simultaneously can be achieved by the WIN 0.15μm pHEMT. The operating frequency of the LNA is 38 GHz, the peak gain is 18.9 dB, minimum noise figure is 2.88dB, OP1dB is 7.92dBm and OIP3 is 16dBm, the power consumption is 152mW, the overall chip size is 2x1mm2.