應用於微機電感測器之低功耗可重組式類比至數位轉換器

Abstract

本論文提出可於標準CMOS 0.18μm 1P6M電路製程下，完成用於微機電感測器之可重組式連續漸進式類比至數位轉換器 (SAR ADC)。於此製程下，可以將此ADC微機電感測器及其讀出電路整合於單晶片上。本論文提出之電路配合不同的慣性感測器應用範圍被設計成可調整解析度9-12位元的功能，利用開關對SAR ADC上的電容陣列做調整，以及多工器選擇所需要通過的不同模式下的信號；另外，為了達到低功耗的要求，數位電路的供應電壓設計在0.9伏特，而類比端為了維持線性度，在12位元模式時將供應電壓設計在1.8伏特，在9-11位元模式時將供應電壓設計在1.2伏特，再利用電壓準位轉換器(Level Shifter)做為兩端的橋梁，避免數位端不必要的功率消耗。最後，以離散傅立葉轉換(DFT)計算出第三個諧波值，並回推出SAR ADC中電容不匹配所產生的誤差值，將其補償回數位碼中，達到較高的電路精確度。 此類比至數位轉換器操作於50kS/s取樣頻率，在9-12位元模式下，實現SNDR分別是51.72、56.54、61.35以及67.07 dB，其對應的ENOB分別為8.31、9.1、9.9以及10.85，功率消耗分別為2.47、2.73、3.55以及7.85 W，等效的figure of merit(FoM)則分別為155.6、99.5、74.3以及85 fJ/conversion-step。

A reconfigurable SAR ADC that can be manufactured and monolithically integrated in the ASIC-compatible 0.18μm 1-poly-6-metal (1P6M) standard complementary metal-oxide-semiconductor (CMOS) process is proposed for micro electro mechanical system (MEMS) sensor applications. It could monolithically integrate with MEMS sensor and sensor’s readout circuit for system on chip. According to various sensing range of inertial sensor applications, this SAR ADC is designed for scalable resolution function from 9 to 12 bits which use switches to adjust the capacitor array of SAR ADC and multiplexer to pass through different modes of signal. In addition, the dual supply voltage skill is implemented for achieving lower power consumption. The supply voltage is set to 0.9 voltage in digital domain and the supply voltage is set to 1.8 voltage (12 bits mode) or 1.2 voltage (9-11 bits mode) in the analog domain for keeping the circuit linearity. The interface between digital and analog is connected by level shifter. Using the discrete Fourier transform (DFT) calibration to deal with the output digital code of SAR ADC through MATLAB software, the third harmonic distortion of the output signal can be calculated and then be used to re-derive the error causing by DAC capacitor mismatch. This calibration technique compensates the error to the output digital code and make higher performance of SAR ADC. The ADC sampling rate, about ten times larger than frequency of the sensor input signal, operates at 50 kS/s. With 9 to 12 bits modes, the ADC achieves SNDR to 51.72, 56.54, 61.35 and 67.07 dB respectively and the corresponding ENOB are 8.31, 9.1, 9.9 and 10.85 respectively and consumes 2.47, 2.73, 3.55 and 7.85 μW respectively, It results the FoM to be 155.6, 99.5, 74.3 and 85 fJ/conversion-step respectively.