標題: 應用於複合性功能感測單晶片之三角積分類比數位轉換器
Sigma-Delta Analog to Digital convertor for multi-sensor SOC
作者: 劉志峻
Liu, Chih-Chun
溫瓌岸
Wen, Kuei-Ann
電子工程學系 電子研究所
關鍵字: 複合性感測器;高動態範圍;高解析度;兩級運算放大器;Multi-sensor;High Dynamic Range;High Resolution;Two Stage OPAMP
公開日期: 2013
摘要: 於本篇論文中,將設計一高解析度Analog to Digital converter,供給Multi-Sensor SOC使用。由於目前訊號頻寬為尚處於基頻頻段,且為了追求高解析度之Performance,故在此選擇 ”三階前饋離散式三角積分調變器”(SDM)進行設計,且將OSR(Over-sampling Rate)提高至256,令其實現。 由於在三階SDM之設計中,除了考量電路非理想效應之外,還涉及穩定度之議題,因此將在電路設計之前,先於MATLAB中建立等效Behavioral Model,用以縮短電路於Spectre中冗長的模擬時間。在此以TSMC 0.18um CMOS MEMS Process下將其實現,此時設計規格之頻寬1KHz,電路經由設計後於1.8V電壓下,消耗424uW之功率散逸,此時Chip Area(含PAD)為1980x960um^2,SQNR為90.9dB,DR為94dB,Resolution達至14bits。
In the thesis, we design a high resolution Analog to Digital converter for Multi-sensor SOC. Due to low bandwidth of MEMS applications, the three order feed-forward type SDM is adopted. For high resolution of MEMS application, and it can achieve to 256 of OSR. When the three order SDM is designed, the non-ideal effect and system stability need to be considered. Therefore, we establish an equivalent behavioral model in MATLAB before circuit design. The behavioral model can help reduce the duration of circuit level simulation. The bandwidth of design specification is 1 KHz under 1.8V of power supply. Finally, it’s power dissipation is 424uW. Chip Area with PAD is 1980x960um^2. The performance of SQNR and DR are 90.9 dB and 94.9 dB respectively, and the resolution of proposed design is 14 bits.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079911659
http://hdl.handle.net/11536/73732
顯示於類別:畢業論文