在通電後錫晶粒方向與錫晶界對銅鎳錫介金屬化合物成長的影響

Abstract

隨著科技日新月異，以及使用上的現實需求，尺寸的微縮已成為趨勢，特別是可攜式及高性能需求的微電子產品，都往輕、薄、短、小、耐摔的目標邁進，而覆晶銲錫則成為達成此目的的最佳製造方式之一。覆晶銲錫技術不但可以提高面積使用率，比傳統的打線銲錫多出數十倍的In/Out put數量；更可以縮短製程時間，甚至能降低業界在意的製造成本。覆晶銲錫的技術目前已經廣泛應用在高散熱需求的高階電腦設備，以及高性能、高密度的In/Out put數，例如精密的通訊產品、可攜式的消費性電子產品、汽車零件等，因其需要高In/Out put數及高的訊號傳輸品質與能通過嚴苛之溫度/濕度/振動及電磁干擾；對於液晶螢幕(Liquid Crystal Display, LCD)越來越小的體積與重量需求，覆晶銲錫也都可以滿足這樣的需要。 本論文所研究的是，利用銅鎳覆晶銲錫試片探討不同的電流密度下，電遷移的破壞模式，觀察銅鎳錫介金屬化合物(Intermetallic Compounds, IMCs)的差異。先觀察電阻值變化，再確認微結構經過通電後的結果，錫晶粒的方向是利用電子背向散射繞射儀(Electron Backscatter diffraction, EBSD)來分析。其電流大小使用了0.9安培的1倍、2倍、2.5倍做為測試條件，電流密度分別為5.45 x 103 A/cm2、1.09 x 104 A/cm2 、1.36 x 104 A/cm2 ，雖然一般對銅和鋁要造成電遷移破壞的電流密度為105~106 A/cm2，但本實驗加上溫度與時間的反應，來進一步觀察銲錫凸塊中之錫晶粒變化。 本研究發現同樣施加電流為0.9安培的試片，較低溫者130℃試片經過3000小時的通電測試，可析出些許大角度的錫晶粒，但同樣條件的150℃試片，則已有介金屬化合物生成。然而外加電流增加至2.25安培的試片，經過1600小時的電遷移後，已生成了較穩定的介金屬化合物。從實驗中也證實，若銲錫中錫晶粒本身角度會對電遷移的阻抗有較大的影響，若銲錫中錫晶粒角度較大的話，比較容易阻擋電遷移，使其在經過長時間的破壞後，仍可保有晶粒狀態，電阻變化也相對小許多。但反之，若本身錫晶粒角度較小，經過電遷移後，則容易形成銅錫的介金屬化合物，同時其所造成的電阻變化率較明顯；假設已經破壞到形成空孔，則電阻變化率將會是最高的。另外，電子流向下的銲錫，在銅與銲錫之間多了一層鎳薄膜，由電阻變化數據可以觀察到，有這層薄膜能延緩電遷移的影響，達到元件保護的效果。

With the ever-changing nature of technology and the needs of practical use, miniaturization of dimension has become an emerging trend. This is especially shown in the advance of portable and high-performance microelectronics products, which go in quest of lighter, slimmer, shorter, smaller, and shatterproof design. To achieve this goal, manufacture by using flip-chip solder is one of the best solutions. This technique not only significantly increases the area utilization ratio, but also shortens production timeline and reduces costs when comparing to regular wire bonding. It has been widely used in high-end electronic equipment which is of greater efficiency, intensive I/O module and advanced thermal design. These include, for example, communication apparatus with stringent demands of quality transmission and I/O design, portable consumer electronics that consist of high-density components, car parts that resist dramatic changes of temperature, humidity, and vibration, and LCD driver IC that is in smaller dimensional specification. This study aims to investigate the changes of intermetallic compounds (IMCs) on Cu-Sn flip chip solder bumps under various current densities in a model of electromigration failure. We study variance in electric resistance and composition of the micro structure, and further analyze its Sn grain orientation by Electron Backscatter Diffraction (EBSD). We set current at 0.9 A, 1.8A, 2.25A as experiment conditions to achieve current density of 5.45 x 103 A/cm2, 1.09 x 104 A/cm2, 1.36 x 104 A/cm2, respectively. Although inducing electromigration failure requires 105 ~ 106 A/cm2, we took temperature and test duration as variables, by which allowing us to observe changes of the Sn grain effect in the solder bumping in a comprehensive manner. In condition of 0.9 A current and 3000 hours duration, while using a sample of 130oC we were able to observe few Sn grain with high-angle boundary, using a sample of 150 oC we found IMCs generation. Interestingly, stable IMCs were formed by increasing the current to 2.25 A for 1600 hours. In this study, we demonstrated that Sn grain’s boundary significantly impacts the resistance of electronic migration. With high-angle grain boundary, it blocked electronic migration and kept its grain state more easily, resulting in lesser electrical resistance changes even after a long-term damage treatment. In contrast, low-angle grain boundary was liable to form IMCs after electronic migration, causing high electrical resistance. The highest electrical resistance was observed when holes form by serious damages. In addition, a nickel film was generated between the Cu and Sn bumps in the e-down set. We found that this film eliminated electric damage and was able to protect device components.