标题: | 鳍状式场效电晶体之特性分析及堆叠式环状闸极场效电晶体于逻辑电路应用中最佳堆叠层数之探讨 Characterization of FinFETs and Investigation of the Optimum Stacking Number of Stacked Nanowire FETs for Logic Applications |
作者: | 黄威程 苏彬 Huang, Wei-Cheng Su, pin 电子研究所 |
关键字: | 环状闸极电晶体;鳍状式电晶体;FinFET;Gate-all-around FET;Nanowire FET |
公开日期: | 2017 |
摘要: | 本论文提出一套新的并且简易的变温量测法(Hot chuck measurement)来萃取热电阻(Thermal resistance),利用去除寄生电阻(Parasitic resistance)后的本质互导(Intrinsic transconductance)作为因为自我加热效应(Self-heating effect)而产生元件变温的感测参数,此方法只需要直流量测(DC measurement),并且对于特殊的测试元件(Test pattern)没有需求。除此之外,考量5奈米的技术节点(Technology node)对于逻辑电路应用中堆叠式环状闸极电晶体(Gate-all-around Nanowire FETs)的最佳会堆叠层数进行探讨。我们研究指出接触电阻率(Contact resistivity)对于堆叠是关键的,垂直间隔距离(Vertical pitch)因为影响寄生电容(parasitic capacitance)同样重要。我们的研究指出以空气作为间隔介电层(Air spacer)对于逻辑电路表现的提升有最大的帮助。 This thesis proposes a new and simple hot-chuck measurement method for the extraction of the thermal resistance of FinFETs. The intrinsic transconductance that eliminates the parasitic source/drain resistance effect can serve as a temperature sensor to characterize the device temperature rise due to self-heating. Our method requires only DC measurements without the need of specific test patterns. In addition, based on 5-nm technology node, we have investigated the optimum stacking number for vertically stacked nanowire FETs. Our study indicates that the contact resistivity is crucial to the optimum stacking number. The vertical pitch of nanowires is also crucial to the optimum stacking number due to the parasitic capacitance. Our study indicates that air spacer may be the most efficient method to improve the logic performance of the nanowire FETs. |
URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070450145 http://hdl.handle.net/11536/142811 |
显示于类别: | Thesis |