鰭狀式場效電晶體之特性分析及堆疊式環狀閘極場效電晶體於邏輯電路應用中最佳堆疊層數之探討

Abstract

本論文提出一套新的並且簡易的變溫量測法(Hot chuck measurement)來萃取熱電阻(Thermal resistance)，利用去除寄生電阻(Parasitic resistance)後的本質互導(Intrinsic transconductance)作為因為自我加熱效應(Self-heating effect)而產生元件變溫的感測參數，此方法只需要直流量測(DC measurement)，並且對於特殊的測試元件(Test pattern)沒有需求。除此之外，考量5奈米的技術節點(Technology node)對於邏輯電路應用中堆疊式環狀閘極電晶體(Gate-all-around Nanowire FETs)的最佳會堆疊層數進行探討。我們研究指出接觸電阻率(Contact resistivity)對於堆疊是關鍵的，垂直間隔距離(Vertical pitch)因為影響寄生電容(parasitic capacitance)同樣重要。我們的研究指出以空氣作為間隔介電層(Air spacer)對於邏輯電路表現的提升有最大的幫助。

This thesis proposes a new and simple hot-chuck measurement method for the extraction of the thermal resistance of FinFETs. The intrinsic transconductance that eliminates the parasitic source/drain resistance effect can serve as a temperature sensor to characterize the device temperature rise due to self-heating. Our method requires only DC measurements without the need of specific test patterns. In addition, based on 5-nm technology node, we have investigated the optimum stacking number for vertically stacked nanowire FETs. Our study indicates that the contact resistivity is crucial to the optimum stacking number. The vertical pitch of nanowires is also crucial to the optimum stacking number due to the parasitic capacitance. Our study indicates that air spacer may be the most efficient method to improve the logic performance of the nanowire FETs.