適用於雙耳助聽器之低延遲降噪演算法與硬體實作

Abstract

我們實現一個低延遲且即時的降噪(Noise reduction)演算法。此演算法接在雙輸出腳位的實數快速傅利葉轉換器的後面，並適用於雙耳助聽器。我們在頻域上利用雙耳線索(Binaural cues)和最小值控制遞回平均法(Minima controlled recursive average)產生方向性遮罩(Directional mask)與預估遮罩(Estimated mask)。方向性遮罩主要用來消掉側邊的雜訊，由其是人聲，使用的方法包含雙耳時間差(Interaural time difference, ITD)線索與雙耳能量差(Interaural level difference, ILD)線索。而最小值控制遞回平均主要用來消掉正前方的背景雜訊與散射雜訊。 為了使硬體面積下降，我們提出減少儲存面積的方法，由於快速傅利葉轉換的點數遠高於時域輸入的點數，造成頻域精準度(resolution)過度分析。我們在頻域只取出需要的頻率點來運算遮罩(mask)，而其它頻域的遮罩則由這些支持頻域點算出的遮罩複製過去。此法大幅降地硬體所需要的面積，因為所需要存取的資料量減少許多。 軟體模擬結果發現我們的降噪演算法使訊號失真比(Signal to Distortion Ratio, SDR)、源與干擾比(Source to Interference Ratio)、語音清晰度指數(Speech Intelligibility Index, SII)和短時客觀清晰度(Short-Time Objective Intelligibility, STOI)分別提升平均約2.03 dB、7.92dB、0.13和0.04。我們的降噪演算法實現在TSMC 90奈米CMOS高臨界電壓製成單元庫(cell library)。硬體設計在13MHz時脈下，消耗約381 μW (工作電壓0.9伏特)，面積約為266288閘數。

We implement a low-latency and real-time noise reduction algorithm based on two-port Real-valued Fast Fourier Transform (RFFT) architecture for binaural hearing aids. The directional mask and estimated mask are obtained by using binaural cues and minima controlled recursive average method respectively. The directional mask is main to cancel noises from lateral especially for interference noise. It exploits the interaural time difference (ITD) and the interaural level difference (ILD) together. Furthermore, background and diffuse noises ahead are reduced by estimated mask. In order to optimize the area of hardware, we propose a method to minimize the memory. Since that the points of RFFT are much more than input data points, it cause an over-resolution analysis phenomena. For the reason, we only analyze the sufficient frequency (Support Frequency) points to calculate the mask while the masks of other frequency are copy from those sufficient mask. In this way, the data stored in register file decrease a lot. Also, the area of NR is highly cut down. The simulation results show that our NR algorithm can improve Source to Distortion Ratio (SDR), Source to Interference Ratio (SIR), Speech Intelligibility Index (SII) and Short-Time Objective Intelligibility (STOI) about 2.03dB, 7.92dB, 0.13, and 0.04 respectively. It has been implemented in TSMC 90 nm CMOS high-VT technology operated by 13MHz and consuming about 381 μW (@0.9V). And the area is about 266288 gate counts.