效率改進之2.4 GHz SiGe HBT 功率放大器

Abstract

本篇論文主要分成兩個主題，包含了消除交互調變失真項以提升2.4 GHz雙模態功率放大器的線性度，以及實現具有Watt-Level高效率之全積體化2.45 GHz疊接功率放大器。 第一部分使用TSMC 0.18-μm SiGe BiCMOS製程實現2.4 GHz雙模態功率放大器，利用改變電晶體顆數的方式改善低功率輸出時的效率，並且使用四分之波長週期性特性消除交互調變失真訊號，提升功率放大器的線性度，並將其實現於PCB FR-4板上。 第二部分使用TSMC 0.18-μm SiGe BiCMOS製程實現Watt-Level高效率2.45 GHz疊接功率放大器，利用疊接架構提升最佳輸出阻抗，並且實現具有高線性度、高效率以及高度積體化的目標。

This thesis consists of two parts, including eliminating the intermodulation distortion to enhance the linearity of a 2.4 GHz dual-mode power amplifier and realizing a Watt-Level high-efficiency 2.45 GHz stacked power amplifier with a fully integrated design. In the first part, a 2.4 GHz dual-mode power amplifier which improves the efficiency at low-power region by the physical-size reduction method using TSMC 0.18-μm SiGe BiCMOS process is presented; moreover, the linearity is enhanced by utilizing a quarter-wave length bias implemented on a PCB FR-4 to eliminate the intermodulation distortion. In the second part, a Watt-Level high-efficiency 2.45 GHz stacked power amplifier is demonstrated using TSMC 0.18-μm SiGe BiCMOS process. The stacked structure is used to increase the optimized output impedance, hence achieving the goals of high-efficiency, high-linearity, and high-integrated level as well.