標題: Tri-gated Poly-Si Nanowire SONOS Devices
作者: Hsu, Hsing-Hui
Liu, Ta-Wei
Lin, Chuan-Ding
Chia Kuo-Jung
Huang, Tiao-Yuan
Lin, Horng-Chih
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [ 1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.
URI: http://hdl.handle.net/11536/14311
ISBN: 978-1-4244-2784-0
期刊: PROCEEDINGS OF TECHNICAL PROGRAM: 2009 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS
起始頁: 148
結束頁: 149
Appears in Collections:Conferences Paper