Tri-gated Poly-Si Nanowire SONOS Devices

Abstract

Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [ 1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.