高效能之漣波調變導通時間控制之降壓電源轉換器

Abstract

本論文實現一高效能之漣波調變導通時間控制之降壓電源轉換器(ripple-based on-time controlled buck converter)，有鑑於大電流的驅動能力與快速地暫態反應的優勢，此控制方法渴望被廣泛應用於可攜式產品之晶片系統的電源管理模組；然而，較大輸出電壓漣波(output voltage ripple)與變動的操作頻率(switching frequency)，是目前學術產業界尚須解決的兩個課題。較大輸出電壓漣波使得後端的先進製程電路的操作電壓超過規範值，變動的操作頻率降低效能並且受到電磁干擾(electromagnetic interference (EMI))。本論文為漣波調變導通時間控制提出的技術包含兩個部分，第一部分為漣波重整技術(ripple reshaping technique)，透過雙模漣波還原補償器(dual-mode ripple-recovered compensator (D-RRC))與雜訊邊限提升電路(noise margin enhancement (NME))針對負回授的訊號做處理，使電路可接受使用較低等效串聯電阻(equivalent series resistance (ESR))的輸出電容，達到系統穩定的穩壓效能，並且有抑制等效串聯電感(equivalent series inductance (ESL))干擾的技術，將傳統利用鉭質輸出電容(Tantalum capacitor)達到穩定的方法，替換成積層陶瓷電容(multi-layer ceramic capacitor (MLCC))，達到低輸出漣波電壓並且有高穩壓效能的優點，同時更可以降低電容元件成本。本論文所提出的另一個技術為擬定頻操作頻率 (pseudo-constant switching frequency)，本論文為操作頻率與其寄生效應提供完整分析，透過所提出低複雜的模型設計最佳化導通時間控制器(optimum on-time controller)，去除傳統所需的精準的元件特性資訊與複雜的量測技術，亦在不需要固定時脈訊號(clock signal)下，於輸入電壓(input voltage)、輸出電壓(output voltage)、負載(load)的變化下，最佳化導通時間控制器可以轉換等效的責任週期(duty cycle)調整最佳的導通時間長度，保持固定的操作頻率。因此，本論文所提出的技術兼顧原有的大電流驅動能力與快速暫態反應的優勢，並達到低漣波輸出電壓與固定操作頻率的改良，實現高效能的漣波調變導通時間控制之降壓電源轉換器。在實驗結果中驗證漣波重整技術與擬定頻操作頻率的正確性與高性能，電路可容忍約1mΩ等效串聯電阻保持系統穩定並產生低於6mV的低漣波輸出電壓，在2.5MHz的操作頻率下且負載1.4安培的變化下保持低於8kHz的操作頻率變化。此外，能量轉換效率最高可達到超過90%，符合晶片系統電源管理模組整合的要求。

This dissertation presents a high-performance ripple-based on-time controlled buck converter. Ripple-based on-time controllers have the advantages of high current-driving capability and fast transient response, features that enable their application to the power management of system-on-a-chip (SoC) in portable devices. However, the disadvantages of large output voltage ripple and variable switching frequency (fSW) are two significant challenges for high-quality power supply. This dissertation proposes a ripple reshaping technique and an optimum on-time controller to mitigate the drawbacks. The first part of this dissertation presents a ripple reshaping technique that includes a dual-mode ripple-recovered compensator (D-RRC) and noise margin enhancement (NME) to achieve small output voltage ripples even if multilayer ceramic capacitors (MLCCs) are used. D-RRC eliminates the conventional stability problem, which is determined by the sufficiently large time constant of output capacitance and its equivalent series resistance (ESR). Therefore, the subharmonic problem can be avoided, and an MLCC with a small ESR for small output voltage ripple can be used. Moreover, NME improves robust stability by increasing the tolerance of the equivalent series inductance effect. The analysis of fSW is also presented and the parasitic resistances are all considered. A low-complexity model and an optimum on-time controller are proposed to achieve pseudo-constant fSW under different input voltage, output voltage, and loading current conditions. As a result, parasitic resistances almost have no influence and restriction on the pseudo-constant fSW. Extra clock-controlled circuits and current-sensing circuits used in conventional designs are unnecessary. Only input voltage is used to predict the optimum on-time, which indicates the reduction of pin numbers. Measurement results show that ∆fSW/fSW is only 0.32% and ∆fSW/∆ILOAD is 5.7 kHz/A in the case of a 1.4 A load current change and a 2.5 MHz fSW. Consequently, a pseudo-constant fSW with a well-defined noise spectrum strongly benefits the solution of electromagnetic interference for SoC applications.