三維積體電路玻璃穿孔與矽穿孔之研究與比較

Abstract

摘 要 隨著摩爾定律的推進，如何縮短電訊號間距離與降低電阻電容所造成的延遲時間成了現今重要議題。透過三維垂直堆疊使用玻璃穿孔與矽穿孔導線取代傳統接線，可有效利用空間並解決上述問題。而本論文提出的玻璃穿孔擁有低成本、良好電性之特性，是取代傳統接線的最佳方案之一。 論文的第一部分介紹玻璃穿孔導線的製程步驟，探討製程中所遇到的問題如:玻璃穿孔電鍍不均勻、以及有V型形狀的凹洞形成於玻璃穿孔填銅處。透過光學顯微鏡、X光斷層掃描和掃描式電子顯微鏡進行結構與製程分析，改良製程並找出解決方案。最後提出最佳化製程，完成高均勻度且無空隙的玻璃穿孔導線與矽穿孔導線。 論文的第二部分進行電性分析與可靠度測試，電性分析包括單根玻璃/矽穿孔導線電阻值、多根玻璃/矽穿孔導線電阻值、多根玻璃/矽穿孔導線漏電流、多根玻璃/矽穿孔導線耦合電容值。其中玻璃穿孔導線比矽穿孔導線有更低的漏電流，顯示出玻璃穿孔導線擁有較佳的絕緣特性。透過多根玻璃/矽穿孔導線電阻值，得到電阻與穿孔數量間穩定的線性關係，代表玻璃/矽穿孔導線與線路重佈之間有連續且穩固的連接。 最後，經過可靠度測試如:溫度循環及濕度測試之後，電阻與穿孔數量間仍然保持的線性關係，證明透過最佳化製程製作出的玻璃/矽穿孔導線在未來3D垂直堆疊應用中可提供良好可靠度的連接。

With the advancement to keep up with Moore's Law, ways to shorten the distance between the electrical signals and reduce the R-C delay have become important. With 3D vertical stacking using through glass via (TGV) and through silicon via (TSV) as interconnects to replace the traditional wiring connection, we can solve the issues mentioned above and utilize space more efficiently. TSV is one of the key technologies for 3D-IC integration. While silicon has been conventionally used in this application, glass has an excellent insulating property that makes it very suitable for through substrate via applications. Because of the good insulating property of glass, the leakage of multiple TGV is much lower than the leakage of multiple TSV under same conditions. Besides that, without depositing the insulation layer, we can further reduce the manufacturing cost. TGV, with fewer process steps, lower cost and excellent electrical properties, is one of the best solutions to replace traditional wiring connection. In the first part of the thesis, one sealing redistribution layer (RDL) with bottom-up Cu TSV plating method is proposed. However, this method includes some drawbacks, such as uneven TGV plating and V-shape pits formed near TGV. These issues are examined by structure and process analysis with OM, X-ray, P-10 (surface profiler), and SEM analysis. The process flow is further improved by sealing via with photoresist (PR) or tape. As a result, the optimized bottom-up plating method defined as “sealing RDL before bottom-up plating” can change the process order of TGV/TSV and RDL formation by sealing the RDL formation first before using bump-up plating to form TGV/TSV. From the improved process flow, the high uniformity and void-free copper filling of TGV/TSV with an aspect ratio of 4 via copper electroplating is also successfully achieved. Thus, the reliability of the TGV/TSV can be greatly improved. The optimized process has been successfully demonstrated on chip-level with 50µm TGV/TSV and 200µm thinned wafers. In the second part of the thesis, Kelvin structure, daisy chain, and comb structure are fabricated for electrical measurements of single TGV/TSV resistance, multiple TGV/TSV resistance, multiple TGV/TSV leakage, and multiple TGV/TSV coupling capacitance. Excellent electrical performances are shown in these measurements. Finally, reliability tests such as humidity test (HAST) and thermal cycle test (TCT) are performed to inspect the quality of daisy chain structure. The results show good stability without significant variation. With excellent electrical and reliability results, through glass via (TGV) fabricated by optimized process is suitable for future 3D vertical interconnects.