奈米積體電路CMOS製程之先進靜電放電防護設計

Abstract

為了達到更低的功率消耗、更高的操作效率及更佳的積體電路整合能力，互補式金氧半製程以持續微縮元件為目標，不僅降低操作電壓，也微縮閘極氧化層和通道長度。但是，當元件微縮進入奈米製程後，元件尺寸變得更細微的情況下，閘極漏電流變成了最嚴重的可靠度議題之一。當電晶體內的閘極氧化層只有數個奈米的厚度時，因電子透過穿隧效應穿過氧化層的機率提高而使閘極穿隧電流劇烈增加，導致這個現象無法被忽視。由於薄閘極氧化層也擁有低崩潰電壓之特性，使得先進製程之靜電放電防護設計更具有挑戰性。在傳統製程的靜電放電防護設計中，常以大面積的金氧半電晶體作為主要靜電放電箝制電路和偵測靜電放電的電容元件。但由於在先進製程中具有高閘極漏電流之特性，這樣子使用大面積金氧半電晶體的傳統設計，將會消耗更多的功率，不利於低功耗電路之應用。此外，一些傳統設計可能會因閘極漏電流造成顯著的壓降，使防護電路無法適當運作，因而失去防護能力。過去已有文獻針對如何降低閘極漏電流影響的議題進行研究探討。一些已被提出的設計雖然能夠有效地降低靜電放電防護電路的漏電流，但有增加佔用佈局面積的缺點。由於在先進製程中單位面積的製程成本非常昂貴，因此增加佈局佔用面積意味著增加高額的晶片製造成本，這使得佔用大面積的靜電放電防護電路變得更加昂貴。因此，如何設計出降低佈局佔用面積並同時減少漏電流之靜電放電防護電路，即為本論文之主要研究主題。 在全晶片靜電放電防護設計架構之中，靜電放電箝制電路能夠在靜電放電轟擊時 ，提供有效率的電流泄放路徑。在一個良好的靜電放電防護安排擺置中，其靜電放電耐受能力主要由靜電放電箝制電路所決定。但是，由於傳統設計使用了大面積的電容元件去偵測靜電放電轟擊之快速暫態電壓電流特性，在先進製程中往往因此而造成更嚴重的閘極漏電流。因此，在本論文中的第二章提出了一個不需要使用電容元件的新型靜電放電暫態偵測電路，這同時解決了閘極漏電流與佔地面積的問題。另外，這個防護電路內的觸發反相器也因為加入串接二極體而進一步改善閘極漏電流和氧化層可靠度的問題，且僅只因二極體而多消耗了些許的佈局佔地面積。 除了於第二章提出的偵測電路，本論文第三章提出了另一種新型的靜電放電暫態偵測電路。在此新型暫態偵測電路中，電容元件的佔地面積因為使用了電容倍升電路而被大幅減少。此電容倍升電路是由一個電流鏡串接著一個電容元件，藉由放大它的電流值，進而放大其等效電容值。藉由此電路技巧與數學公式分析，此靜電放電暫態偵測電路的佈局佔地面積能被大幅縮小。另外，一個具有嵌入式觸發的矽控整流器也被提出並運用於此靜電放電防護電路，此矽控整流器也能進一步減少防護電路的佈局佔地面積，降低晶片製造成本。 目前發展的系統單晶片積體電路為了符合設計需求，其系統具有多種電壓準位和不同功能之積體電路。為了確保不同電路區塊間也能擁有良好的靜電放電泄放路徑，在不同區塊間需要設計具備雙向導通能力的靜電放電箝制電路。而為了達到上述目的，背對背的二極體結構是典型上常被使用的其中一種防護設計，但此設計往往需要佔用一定的佈局面積，且可能因為有串接數個二極體而造成過大的漏電流。本論文第四章提出了一個具備雙向導通能力的新型靜電放電箝制電路，主要使用雙向矽控整流器來實現，並使用了新型的對稱式靜電放電偵測電路和觸發電路來控制雙向矽控整流器的導通，此電路設計主要專注於漏電流的改善和減少佈局的佔地面積。 典型的積體電路會在輸出輸入介面和內部電路各別使用不同的電壓準位以符合設計需求。另外，輸出輸入介面和內部電路的接地線也會各別獨立，藉以避免雜訊干擾。由於此兩個電源區塊是分離的，當晶片遭受靜電放電轟擊時，容易在其接面電路造成損傷。因此，除了擺置靜電放電防護元件在各自的電源區塊內，額外的靜電放電防護元件也必須擺置在區塊間的接面電路，但此設計也將增加佈局佔地面積。本論文第五章提出了一個以矽控整流器為主的新型靜電放電防護元件，此設計不僅能做為自身電源區塊的靜電放電防護元件，也能針對不同電源區塊間的接面電路進行防護。相較於傳統設計架構，本論文提出之新型元件能大幅降低佔地面積。

In order to achieve lower power consumption, higher operating speed, and higher integration capability, the CMOS features were continually scaled down with lower operating voltage, thinner gate oxide thickness, and smaller channel length in CMOS technology. However, when the CMOS technologies reached nanoscale dimensions, the gate leakage started becoming a serious issue. When transistors are fabricated with gate oxide of only a few nanometers thick, the gate-oxide-silicon direct tunneling current increases drastically, and thus it cannot longer be ignored. Combined with the increasingly low breakdown voltage, also as result of the thinner the gate oxide, the ESD protection design has become ever more challenging. Traditional ESD protection designs rely heavily in the use of large MOS transistors, used as ESD clamp and also as capacitors (used to detect ESD-like transients). Because of the large gate leakage current, such designs become very inefficient and undesirable for low-power applications. Moreover, some designs may become inoperative due to large voltage drops in the internal circuitry as result of the gate leakage. Previous research effort was focused on the reduction of the leakage current to acceptable levels. Some designs were proposed that effectively reduce the leakage current of the ESD protection circuits, but with an increase in the required silicon area as side effect. As result, due to the increase in fabrication cost per area in the advanced CMOS processes and enlarged area of the ESD protection circuits, ESD protection became more expensive. Therefore, research effort needs to be focused towards area minimization as well as leakage current reduction. Within the whole-chip ESD protection design scheme, the ESD clamp circuit will provide an effective ESD current discharging path under ESD stresses. In a good ESD protection arrangement, the ESD robustness is mainly decided by the ESD clamp circuit. However, the traditional design suffered the serious gate leakage issue in nanoscale CMOS processes due to a large capacitor used to detect the fast transient characteristic of ESD stresses. This capacitor also resulted in very large silicon footprints. Chapter 2 presents a level sensitive ESD detection circuit which does not use such capacitor, thus solving the leakage current and large silicon footprint issues. In addition, the ESD clamp trigger inverter was improved by adding diodes in series with the trigger transistors in order to further reduce the leakage current and increase the gate oxide reliability of such transistors, at the expense of a little area overhead due to the extra diodes added to the circuit. In addition to the level sensitive ESD detection circuit presented in Chapter 2, a transient sensitive ESD detection circuit is introduced in Chapter 3. In this case, the capacitor area is reduced by using a circuital technique known as capacitance boosting, which uses a current mirror connected in series to the capacitor to amplify its current, thus also amplifying the equivalent capacitance. By using this technique and mathematical analysis, the required silicon area of the ESD detection circuit can be minimized. In addition, a technique to fabricate an SCR with embedded trigger is presented, which can further reduce the silicon footprint of the ESD clamp circuit. Nowadays system-on-chip (SoC) ICs integrate circuits with different voltage levels. To ensure adequate ESD protection between the different IC blocks, ESD clamps with bidirectional functionality are often required. Typically, back-to-back diode (strings) were used to achieve this functionality, at the expense of large silicon footprint and somehow large leakage currents in the diode strings. Chapter 4 presents a bidirectional ESD protection circuit based on a dual SCR, which uses a novel symmetrical ESD detection and trigger circuit to control the dual SCR. This circuit is designed with focus on leakage current reduction as well as keeping a small silicon footprint. Typical ICs use different voltages for the IO and internal circuits. In addition, the ground lines are separated to avoid noise coupling between IO and internal circuits. As a result, these two power domains are separated, and thus the interface circuits become sensitive to ESD-related failure. Therefore, besides the ESD protection elements in each power domain, extra ESD protection elements are added between the power domains, thus increasing the required silicon area. Chapter 5 presents an ESD protection device embedding 4 SCRs that can fully protect the interface between two separated power domains, thus reducing the silicon footprint of the ESD protection elements.